diff -u --recursive --new-file linux-2.4.26/Documentation/Configure.help linux-2.4.26.patch/Documentation/Configure.help --- linux-2.4.26/Documentation/Configure.help 2004-04-14 06:05:24.000000000 -0700 +++ linux-2.4.26.patch/Documentation/Configure.help 2004-04-21 09:15:12.000000000 -0700 @@ -11935,6 +11935,16 @@ say M here and read . The module will be called sungem.o. +Broadcom NetXtreme BCM5700 Gigabit Ethernet support +CONFIG_NET_BROADCOM + Say Y here if you have a Broadcom BCM57xx, or 3Com + 3C996/3C997/3C1000/3C940 PCI/PCIX Gigabit Ethernet adapter. + + If you want to compile this driver as a module ( = code which can be + inserted in and removed from the running kernel whenever you want), + say M here and read Documentation/modules.txt. This is recommended. + The module will be called bcm5700.o. + Broadcom Tigon3 support CONFIG_TIGON3 This driver supports Broadcom Tigon3 based gigabit Ethernet cards. diff -u --recursive --new-file linux-2.4.26/drivers/net/bcm/5701rls.c linux-2.4.26.patch/drivers/net/bcm/5701rls.c --- linux-2.4.26/drivers/net/bcm/5701rls.c 1969-12-31 16:00:00.000000000 -0800 +++ linux-2.4.26.patch/drivers/net/bcm/5701rls.c 2004-06-22 16:07:37.000000000 -0700 @@ -0,0 +1,46 @@ +/******************************************************************************/ +/* */ +/* Broadcom BCM5700 Linux Network Driver, Copyright (c) 2000 - 2003 Broadcom */ +/* Corporation. */ +/* All rights reserved. */ +/* */ +/* This program is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU General Public License as published by */ +/* the Free Software Foundation, located in the file LICENSE. */ +/* */ +/* History: */ +/* */ +/******************************************************************************/ + +#if INCLUDE_5701_AX_FIX + +#include "mm.h" +#include "5701rls.h" + +LM_STATUS LM_LoadRlsFirmware(PLM_DEVICE_BLOCK pDevice) +{ + T3_FWIMG_INFO FwImgInfo; + + FwImgInfo.StartAddress = t3FwStartAddr; + FwImgInfo.Text.Buffer = (PLM_UINT8)t3FwText; + FwImgInfo.Text.Offset = t3FwTextAddr; + FwImgInfo.Text.Length = t3FwTextLen; + FwImgInfo.ROnlyData.Buffer = (PLM_UINT8)t3FwRodata; + FwImgInfo.ROnlyData.Offset = t3FwRodataAddr; + FwImgInfo.ROnlyData.Length = t3FwRodataLen; + FwImgInfo.Data.Buffer = (PLM_UINT8)t3FwData; + FwImgInfo.Data.Offset = t3FwDataAddr; + FwImgInfo.Data.Length = t3FwDataLen; + + if (LM_LoadFirmware(pDevice, + &FwImgInfo, + T3_RX_CPU_ID | T3_TX_CPU_ID, + T3_RX_CPU_ID) != LM_STATUS_SUCCESS) + { + return LM_STATUS_FAILURE; + } + + return LM_STATUS_SUCCESS; +} + +#endif /* INCLUDE_5701_AX_FIX */ diff -u --recursive --new-file linux-2.4.26/drivers/net/bcm/5701rls.h linux-2.4.26.patch/drivers/net/bcm/5701rls.h --- linux-2.4.26/drivers/net/bcm/5701rls.h 1969-12-31 16:00:00.000000000 -0800 +++ linux-2.4.26.patch/drivers/net/bcm/5701rls.h 2004-06-22 16:07:37.000000000 -0700 @@ -0,0 +1,198 @@ +/******************************************************************************/ +/* */ +/* Broadcom BCM5700 Linux Network Driver, Copyright (c) 2000 - 2003 Broadcom */ +/* Corporation. */ +/* All rights reserved. */ +/* */ +/* This program is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU General Public License as published by */ +/* the Free Software Foundation, located in the file LICENSE. */ +/* */ +/* History: */ +/******************************************************************************/ + +typedef unsigned long U32; +int t3FwReleaseMajor = 0x0; +int t3FwReleaseMinor = 0x0; +int t3FwReleaseFix = 0x0; +U32 t3FwStartAddr = 0x08000000; +U32 t3FwTextAddr = 0x08000000; +int t3FwTextLen = 0x9c0; +U32 t3FwRodataAddr = 0x080009c0; +int t3FwRodataLen = 0x60; +U32 t3FwDataAddr = 0x08000a40; +int t3FwDataLen = 0x20; +U32 t3FwSbssAddr = 0x08000a60; +int t3FwSbssLen = 0xc; +U32 t3FwBssAddr = 0x08000a70; +int t3FwBssLen = 0x10; +U32 t3FwText[(0x9c0/4) + 1] = { +0x0, +0x10000003, 0x0, 0xd, 0xd, +0x3c1d0800, 0x37bd3ffc, 0x3a0f021, 0x3c100800, +0x26100000, 0xe000018, 0x0, 0xd, +0x3c1d0800, 0x37bd3ffc, 0x3a0f021, 0x3c100800, +0x26100034, 0xe00021c, 0x0, 0xd, +0x0, 0x0, 0x0, 0x27bdffe0, +0x3c1cc000, 0xafbf0018, 0xaf80680c, 0xe00004c, +0x241b2105, 0x97850000, 0x97870002, 0x9782002c, +0x9783002e, 0x3c040800, 0x248409c0, 0xafa00014, +0x21400, 0x621825, 0x52c00, 0xafa30010, +0x8f860010, 0xe52825, 0xe000060, 0x24070102, +0x3c02ac00, 0x34420100, 0x3c03ac01, 0x34630100, +0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, +0xaf82049c, 0x24020001, 0xaf825ce0, 0xe00003f, +0xaf825d00, 0xe000140, 0x0, 0x8fbf0018, +0x3e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, +0x8f835400, 0x34630400, 0xaf835400, 0xaf825404, +0x3c020800, 0x24420034, 0xaf82541c, 0x3e00008, +0xaf805400, 0x0, 0x0, 0x3c020800, +0x34423000, 0x3c030800, 0x34633000, 0x3c040800, +0x348437ff, 0x3c010800, 0xac220a64, 0x24020040, +0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, +0xac600000, 0x24630004, 0x83102b, 0x5040fffd, +0xac600000, 0x3e00008, 0x0, 0x804821, +0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, +0x8c840a68, 0x8fab0014, 0x24430001, 0x44102b, +0x3c010800, 0xac230a60, 0x14400003, 0x4021, +0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, +0x3c030800, 0x8c630a64, 0x91240000, 0x21140, +0x431021, 0x481021, 0x25080001, 0xa0440000, +0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, +0x8c420a60, 0x3c030800, 0x8c630a64, 0x8f84680c, +0x21140, 0x431021, 0xac440008, 0xac45000c, +0xac460010, 0xac470014, 0xac4a0018, 0x3e00008, +0xac4b001c, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x2000008, +0x0, 0xa0001e3, 0x3c0a0001, 0xa0001e3, +0x3c0a0002, 0xa0001e3, 0x0, 0xa0001e3, +0x0, 0xa0001e3, 0x0, 0xa0001e3, +0x0, 0xa0001e3, 0x0, 0xa0001e3, +0x0, 0xa0001e3, 0x0, 0xa0001e3, +0x0, 0xa0001e3, 0x0, 0xa0001e3, +0x3c0a0007, 0xa0001e3, 0x3c0a0008, 0xa0001e3, +0x3c0a0009, 0xa0001e3, 0x0, 0xa0001e3, +0x0, 0xa0001e3, 0x3c0a000b, 0xa0001e3, +0x3c0a000c, 0xa0001e3, 0x3c0a000d, 0xa0001e3, +0x0, 0xa0001e3, 0x0, 0xa0001e3, +0x3c0a000e, 0xa0001e3, 0x0, 0xa0001e3, +0x0, 0xa0001e3, 0x0, 0xa0001e3, +0x0, 0xa0001e3, 0x0, 0xa0001e3, +0x0, 0xa0001e3, 0x0, 0xa0001e3, +0x0, 0xa0001e3, 0x3c0a0013, 0xa0001e3, +0x3c0a0014, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x27bdffe0, +0x1821, 0x1021, 0xafbf0018, 0xafb10014, +0xafb00010, 0x3c010800, 0x220821, 0xac200a70, +0x3c010800, 0x220821, 0xac200a74, 0x3c010800, +0x220821, 0xac200a78, 0x24630001, 0x1860fff5, +0x2442000c, 0x24110001, 0x8f906810, 0x32020004, +0x14400005, 0x24040001, 0x3c020800, 0x8c420a78, +0x18400003, 0x2021, 0xe000182, 0x0, +0x32020001, 0x10400003, 0x0, 0xe000169, +0x0, 0xa000153, 0xaf915028, 0x8fbf0018, +0x8fb10014, 0x8fb00010, 0x3e00008, 0x27bd0020, +0x3c050800, 0x8ca50a70, 0x3c060800, 0x8cc60a80, +0x3c070800, 0x8ce70a78, 0x27bdffe0, 0x3c040800, +0x248409d0, 0xafbf0018, 0xafa00010, 0xe000060, +0xafa00014, 0xe00017b, 0x2021, 0x8fbf0018, +0x3e00008, 0x27bd0020, 0x24020001, 0x8f836810, +0x821004, 0x21027, 0x621824, 0x3e00008, +0xaf836810, 0x27bdffd8, 0xafbf0024, 0x1080002e, +0xafb00020, 0x8f825cec, 0xafa20018, 0x8f825cec, +0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, +0xaf825cec, 0x8e020000, 0x18400016, 0x0, +0x3c020800, 0x94420a74, 0x8fa3001c, 0x221c0, +0xac830004, 0x8fa2001c, 0x3c010800, 0xe000201, +0xac220a74, 0x10400005, 0x0, 0x8e020000, +0x24420001, 0xa0001df, 0xae020000, 0x3c020800, +0x8c420a70, 0x21c02, 0x321c0, 0xa0001c5, +0xafa2001c, 0xe000201, 0x0, 0x1040001f, +0x0, 0x8e020000, 0x8fa3001c, 0x24420001, +0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, +0xa0001df, 0xae020000, 0x3c100800, 0x26100a78, +0x8e020000, 0x18400028, 0x0, 0xe000201, +0x0, 0x14400024, 0x0, 0x8e020000, +0x3c030800, 0x8c630a70, 0x2442ffff, 0xafa3001c, +0x18400006, 0xae020000, 0x31402, 0x221c0, +0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, +0x2442ff00, 0x2c420300, 0x1440000b, 0x24024000, +0x3c040800, 0x248409dc, 0xafa00010, 0xafa00014, +0x8fa6001c, 0x24050008, 0xe000060, 0x3821, +0xa0001df, 0x0, 0xaf825cf8, 0x3c020800, +0x8c420a40, 0x8fa3001c, 0x24420001, 0xaf835cf8, +0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, +0x3e00008, 0x27bd0028, 0x27bdffe0, 0x3c040800, +0x248409e8, 0x2821, 0x3021, 0x3821, +0xafbf0018, 0xafa00010, 0xe000060, 0xafa00014, +0x8fbf0018, 0x3e00008, 0x27bd0020, 0x8f82680c, +0x8f85680c, 0x21827, 0x3182b, 0x31823, +0x431024, 0x441021, 0xa2282b, 0x10a00006, +0x0, 0x401821, 0x8f82680c, 0x43102b, +0x1440fffd, 0x0, 0x3e00008, 0x0, +0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, +0x64102b, 0x54400002, 0x831023, 0x641023, +0x2c420008, 0x3e00008, 0x38420001, 0x27bdffe0, +0x802821, 0x3c040800, 0x24840a00, 0x3021, +0x3821, 0xafbf0018, 0xafa00010, 0xe000060, +0xafa00014, 0xa000216, 0x0, 0x8fbf0018, +0x3e00008, 0x27bd0020, 0x0, 0x27bdffe0, +0x3c1cc000, 0xafbf0018, 0xe00004c, 0xaf80680c, +0x3c040800, 0x24840a10, 0x3802821, 0x3021, +0x3821, 0xafa00010, 0xe000060, 0xafa00014, +0x2402ffff, 0xaf825404, 0x3c0200aa, 0xe000234, +0xaf825434, 0x8fbf0018, 0x3e00008, 0x27bd0020, +0x0, 0x0, 0x0, 0x27bdffe8, +0xafb00010, 0x24100001, 0xafbf0014, 0x3c01c003, +0xac200000, 0x8f826810, 0x30422000, 0x10400003, +0x0, 0xe000246, 0x0, 0xa00023a, +0xaf905428, 0x8fbf0014, 0x8fb00010, 0x3e00008, +0x27bd0018, 0x27bdfff8, 0x8f845d0c, 0x3c0200ff, +0x3c030800, 0x8c630a50, 0x3442fff8, 0x821024, +0x1043001e, 0x3c0500ff, 0x34a5fff8, 0x3c06c003, +0x3c074000, 0x851824, 0x8c620010, 0x3c010800, +0xac230a50, 0x30420008, 0x10400005, 0x871025, +0x8cc20000, 0x24420001, 0xacc20000, 0x871025, +0xaf825d0c, 0x8fa20000, 0x24420001, 0xafa20000, +0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, +0x8fa20000, 0x8f845d0c, 0x3c030800, 0x8c630a50, +0x851024, 0x1443ffe8, 0x851824, 0x27bd0008, +0x3e00008, 0x0, 0x0, 0x0 }; +U32 t3FwRodata[(0x60/4) + 1] = { +0x35373031, 0x726c7341, 0x0, +0x0, 0x53774576, 0x656e7430, 0x0, +0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, +0x45766e74, 0x0, 0x0, 0x0, +0x0, 0x66617461, 0x6c457272, 0x0, +0x0, 0x4d61696e, 0x43707542, 0x0, +0x0, 0x0 }; +U32 t3FwData[(0x20/4) + 1] = { +0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0 }; diff -u --recursive --new-file linux-2.4.26/drivers/net/bcm/autoneg.c linux-2.4.26.patch/drivers/net/bcm/autoneg.c --- linux-2.4.26/drivers/net/bcm/autoneg.c 1969-12-31 16:00:00.000000000 -0800 +++ linux-2.4.26.patch/drivers/net/bcm/autoneg.c 2004-06-22 16:07:37.000000000 -0700 @@ -0,0 +1,438 @@ +/******************************************************************************/ +/* */ +/* Broadcom BCM5700 Linux Network Driver, Copyright (c) 2000 - 2003 Broadcom */ +/* Corporation. */ +/* All rights reserved. */ +/* */ +/* This program is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU General Public License as published by */ +/* the Free Software Foundation, located in the file LICENSE. */ +/* */ +/* History: */ +/******************************************************************************/ + +#if INCLUDE_TBI_SUPPORT +#include "mm.h" + + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +void +MM_AnTxConfig( + PAN_STATE_INFO pAnInfo) +{ + PLM_DEVICE_BLOCK pDevice; + + pDevice = (PLM_DEVICE_BLOCK) pAnInfo->pContext; + + REG_WR(pDevice, MacCtrl.TxAutoNeg, (LM_UINT32) pAnInfo->TxConfig.AsUSHORT); + + pDevice->MacMode |= MAC_MODE_SEND_CONFIGS; + REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode); +} + + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +void +MM_AnTxIdle( + PAN_STATE_INFO pAnInfo) +{ + PLM_DEVICE_BLOCK pDevice; + + pDevice = (PLM_DEVICE_BLOCK) pAnInfo->pContext; + + pDevice->MacMode &= ~MAC_MODE_SEND_CONFIGS; + REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode); +} + + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +char +MM_AnRxConfig( + PAN_STATE_INFO pAnInfo, + unsigned short *pRxConfig) +{ + PLM_DEVICE_BLOCK pDevice; + LM_UINT32 Value32; + char Retcode; + + Retcode = AN_FALSE; + + pDevice = (PLM_DEVICE_BLOCK) pAnInfo->pContext; + + Value32 = REG_RD(pDevice, MacCtrl.Status); + if(Value32 & MAC_STATUS_RECEIVING_CFG) + { + Value32 = REG_RD(pDevice, MacCtrl.RxAutoNeg); + *pRxConfig = (unsigned short) Value32; + + Retcode = AN_TRUE; + } + + return Retcode; +} + + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +void +AutonegInit( + PAN_STATE_INFO pAnInfo) +{ + unsigned long j; + + for(j = 0; j < sizeof(AN_STATE_INFO); j++) + { + ((unsigned char *) pAnInfo)[j] = 0; + } + + /* Initialize the default advertisement register. */ + pAnInfo->mr_adv_full_duplex = 1; + pAnInfo->mr_adv_sym_pause = 1; + pAnInfo->mr_adv_asym_pause = 1; + pAnInfo->mr_an_enable = 1; +} + + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +AUTONEG_STATUS +Autoneg8023z( + PAN_STATE_INFO pAnInfo) +{ + unsigned short RxConfig; + unsigned long Delta_us; + AUTONEG_STATUS AnRet; + + /* Get the current time. */ + if(pAnInfo->State == AN_STATE_UNKNOWN) + { + pAnInfo->RxConfig.AsUSHORT = 0; + pAnInfo->CurrentTime_us = 0; + pAnInfo->LinkTime_us = 0; + pAnInfo->AbilityMatchCfg = 0; + pAnInfo->AbilityMatchCnt = 0; + pAnInfo->AbilityMatch = AN_FALSE; + pAnInfo->IdleMatch = AN_FALSE; + pAnInfo->AckMatch = AN_FALSE; + } + + /* Increment the timer tick. This function is called every microsecon. */ +// pAnInfo->CurrentTime_us++; + + /* Set the AbilityMatch, IdleMatch, and AckMatch flags if their */ + /* corresponding conditions are satisfied. */ + if(MM_AnRxConfig(pAnInfo, &RxConfig)) + { + if(RxConfig != pAnInfo->AbilityMatchCfg) + { + pAnInfo->AbilityMatchCfg = RxConfig; + pAnInfo->AbilityMatch = AN_FALSE; + pAnInfo->AbilityMatchCnt = 0; + } + else + { + pAnInfo->AbilityMatchCnt++; + if(pAnInfo->AbilityMatchCnt > 1) + { + pAnInfo->AbilityMatch = AN_TRUE; + pAnInfo->AbilityMatchCfg = RxConfig; + } + } + + if(RxConfig & AN_CONFIG_ACK) + { + pAnInfo->AckMatch = AN_TRUE; + } + else + { + pAnInfo->AckMatch = AN_FALSE; + } + + pAnInfo->IdleMatch = AN_FALSE; + } + else + { + pAnInfo->IdleMatch = AN_TRUE; + + pAnInfo->AbilityMatchCfg = 0; + pAnInfo->AbilityMatchCnt = 0; + pAnInfo->AbilityMatch = AN_FALSE; + pAnInfo->AckMatch = AN_FALSE; + + RxConfig = 0; + } + + /* Save the last Config. */ + pAnInfo->RxConfig.AsUSHORT = RxConfig; + + /* Default return code. */ + AnRet = AUTONEG_STATUS_OK; + + /* Autoneg state machine as defined in 802.3z section 37.3.1.5. */ + switch(pAnInfo->State) + { + case AN_STATE_UNKNOWN: + if(pAnInfo->mr_an_enable || pAnInfo->mr_restart_an) + { + pAnInfo->CurrentTime_us = 0; + pAnInfo->State = AN_STATE_AN_ENABLE; + } + + /* Fall through.*/ + + case AN_STATE_AN_ENABLE: + pAnInfo->mr_an_complete = AN_FALSE; + pAnInfo->mr_page_rx = AN_FALSE; + + if(pAnInfo->mr_an_enable) + { + pAnInfo->LinkTime_us = 0; + pAnInfo->AbilityMatchCfg = 0; + pAnInfo->AbilityMatchCnt = 0; + pAnInfo->AbilityMatch = AN_FALSE; + pAnInfo->IdleMatch = AN_FALSE; + pAnInfo->AckMatch = AN_FALSE; + + pAnInfo->State = AN_STATE_AN_RESTART_INIT; + } + else + { + pAnInfo->State = AN_STATE_DISABLE_LINK_OK; + } + break; + + case AN_STATE_AN_RESTART_INIT: + pAnInfo->LinkTime_us = pAnInfo->CurrentTime_us; + pAnInfo->mr_np_loaded = AN_FALSE; + + pAnInfo->TxConfig.AsUSHORT = 0; + MM_AnTxConfig(pAnInfo); + + AnRet = AUTONEG_STATUS_TIMER_ENABLED; + + pAnInfo->State = AN_STATE_AN_RESTART; + + /* Fall through.*/ + + case AN_STATE_AN_RESTART: + /* Get the current time and compute the delta with the saved */ + /* link timer. */ + Delta_us = pAnInfo->CurrentTime_us - pAnInfo->LinkTime_us; + if(Delta_us > AN_LINK_TIMER_INTERVAL_US) + { + pAnInfo->State = AN_STATE_ABILITY_DETECT_INIT; + } + else + { + AnRet = AUTONEG_STATUS_TIMER_ENABLED; + } + break; + + case AN_STATE_DISABLE_LINK_OK: + AnRet = AUTONEG_STATUS_DONE; + break; + + case AN_STATE_ABILITY_DETECT_INIT: + /* Note: in the state diagram, this variable is set to */ + /* mr_adv_ability<12>. Is this right?. */ + pAnInfo->mr_toggle_tx = AN_FALSE; + + /* Send the config as advertised in the advertisement register. */ + pAnInfo->TxConfig.AsUSHORT = 0; + pAnInfo->TxConfig.D5_FD = pAnInfo->mr_adv_full_duplex; + pAnInfo->TxConfig.D6_HD = pAnInfo->mr_adv_half_duplex; + pAnInfo->TxConfig.D7_PS1 = pAnInfo->mr_adv_sym_pause; + pAnInfo->TxConfig.D8_PS2 = pAnInfo->mr_adv_asym_pause; + pAnInfo->TxConfig.D12_RF1 = pAnInfo->mr_adv_remote_fault1; + pAnInfo->TxConfig.D13_RF2 = pAnInfo->mr_adv_remote_fault2; + pAnInfo->TxConfig.D15_NP = pAnInfo->mr_adv_next_page; + + MM_AnTxConfig(pAnInfo); + + pAnInfo->State = AN_STATE_ABILITY_DETECT; + + break; + + case AN_STATE_ABILITY_DETECT: + if(pAnInfo->AbilityMatch == AN_TRUE && + pAnInfo->RxConfig.AsUSHORT != 0) + { + pAnInfo->State = AN_STATE_ACK_DETECT_INIT; + } + + break; + + case AN_STATE_ACK_DETECT_INIT: + pAnInfo->TxConfig.D14_ACK = 1; + MM_AnTxConfig(pAnInfo); + + pAnInfo->State = AN_STATE_ACK_DETECT; + + /* Fall through. */ + + case AN_STATE_ACK_DETECT: + if(pAnInfo->AckMatch == AN_TRUE) + { + if((pAnInfo->RxConfig.AsUSHORT & ~AN_CONFIG_ACK) == + (pAnInfo->AbilityMatchCfg & ~AN_CONFIG_ACK)) + { + pAnInfo->State = AN_STATE_COMPLETE_ACK_INIT; + } + else + { + pAnInfo->State = AN_STATE_AN_ENABLE; + } + } + else if(pAnInfo->AbilityMatch == AN_TRUE && + pAnInfo->RxConfig.AsUSHORT == 0) + { + pAnInfo->State = AN_STATE_AN_ENABLE; + } + + break; + + case AN_STATE_COMPLETE_ACK_INIT: + /* Make sure invalid bits are not set. */ + if(pAnInfo->RxConfig.bits.D0 || pAnInfo->RxConfig.bits.D1 || + pAnInfo->RxConfig.bits.D2 || pAnInfo->RxConfig.bits.D3 || + pAnInfo->RxConfig.bits.D4 || pAnInfo->RxConfig.bits.D9 || + pAnInfo->RxConfig.bits.D10 || pAnInfo->RxConfig.bits.D11) + { + AnRet = AUTONEG_STATUS_FAILED; + break; + } + + /* Set up the link partner advertisement register. */ + pAnInfo->mr_lp_adv_full_duplex = pAnInfo->RxConfig.D5_FD; + pAnInfo->mr_lp_adv_half_duplex = pAnInfo->RxConfig.D6_HD; + pAnInfo->mr_lp_adv_sym_pause = pAnInfo->RxConfig.D7_PS1; + pAnInfo->mr_lp_adv_asym_pause = pAnInfo->RxConfig.D8_PS2; + pAnInfo->mr_lp_adv_remote_fault1 = pAnInfo->RxConfig.D12_RF1; + pAnInfo->mr_lp_adv_remote_fault2 = pAnInfo->RxConfig.D13_RF2; + pAnInfo->mr_lp_adv_next_page = pAnInfo->RxConfig.D15_NP; + + pAnInfo->LinkTime_us = pAnInfo->CurrentTime_us; + + pAnInfo->mr_toggle_tx = !pAnInfo->mr_toggle_tx; + pAnInfo->mr_toggle_rx = pAnInfo->RxConfig.bits.D11; + pAnInfo->mr_np_rx = pAnInfo->RxConfig.D15_NP; + pAnInfo->mr_page_rx = AN_TRUE; + + pAnInfo->State = AN_STATE_COMPLETE_ACK; + AnRet = AUTONEG_STATUS_TIMER_ENABLED; + + break; + + case AN_STATE_COMPLETE_ACK: + if(pAnInfo->AbilityMatch == AN_TRUE && + pAnInfo->RxConfig.AsUSHORT == 0) + { + pAnInfo->State = AN_STATE_AN_ENABLE; + break; + } + + Delta_us = pAnInfo->CurrentTime_us - pAnInfo->LinkTime_us; + + if(Delta_us > AN_LINK_TIMER_INTERVAL_US) + { + if(pAnInfo->mr_adv_next_page == 0 || + pAnInfo->mr_lp_adv_next_page == 0) + { + pAnInfo->State = AN_STATE_IDLE_DETECT_INIT; + } + else + { + if(pAnInfo->TxConfig.bits.D15 == 0 && + pAnInfo->mr_np_rx == 0) + { + pAnInfo->State = AN_STATE_IDLE_DETECT_INIT; + } + else + { + AnRet = AUTONEG_STATUS_FAILED; + } + } + } + + break; + + case AN_STATE_IDLE_DETECT_INIT: + pAnInfo->LinkTime_us = pAnInfo->CurrentTime_us; + + MM_AnTxIdle(pAnInfo); + + pAnInfo->State = AN_STATE_IDLE_DETECT; + + AnRet = AUTONEG_STATUS_TIMER_ENABLED; + + break; + + case AN_STATE_IDLE_DETECT: + if(pAnInfo->AbilityMatch == AN_TRUE && + pAnInfo->RxConfig.AsUSHORT == 0) + { + pAnInfo->State = AN_STATE_AN_ENABLE; + break; + } + + Delta_us = pAnInfo->CurrentTime_us - pAnInfo->LinkTime_us; + if(Delta_us > AN_LINK_TIMER_INTERVAL_US) + { +// if(pAnInfo->IdleMatch == AN_TRUE) +// { + pAnInfo->State = AN_STATE_LINK_OK; +// } +// else +// { +// AnRet = AUTONEG_STATUS_FAILED; +// break; +// } + } + + break; + + case AN_STATE_LINK_OK: + pAnInfo->mr_an_complete = AN_TRUE; + pAnInfo->mr_link_ok = AN_TRUE; + AnRet = AUTONEG_STATUS_DONE; + + break; + + case AN_STATE_NEXT_PAGE_WAIT_INIT: + break; + + case AN_STATE_NEXT_PAGE_WAIT: + break; + + default: + AnRet = AUTONEG_STATUS_FAILED; + break; + } + + return AnRet; +} +#endif /* INCLUDE_TBI_SUPPORT */ + diff -u --recursive --new-file linux-2.4.26/drivers/net/bcm/autoneg.h linux-2.4.26.patch/drivers/net/bcm/autoneg.h --- linux-2.4.26/drivers/net/bcm/autoneg.h 1969-12-31 16:00:00.000000000 -0800 +++ linux-2.4.26.patch/drivers/net/bcm/autoneg.h 2004-06-22 16:07:37.000000000 -0700 @@ -0,0 +1,418 @@ +/******************************************************************************/ +/* */ +/* Broadcom BCM5700 Linux Network Driver, Copyright (c) 2000 - 2003 Broadcom */ +/* Corporation. */ +/* All rights reserved. */ +/* */ +/* This program is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU General Public License as published by */ +/* the Free Software Foundation, located in the file LICENSE. */ +/* */ +/* History: */ +/******************************************************************************/ + + +#ifndef AUTONEG_H +#define AUTONEG_H + + + +/******************************************************************************/ +/* Constants. */ +/******************************************************************************/ + +#define AN_LINK_TIMER_INTERVAL_US 12000 /* 10ms */ + +/* TRUE, FALSE */ +#define AN_TRUE 1 +#define AN_FALSE 0 + + + +/******************************************************************************/ +/* Main data structure for keeping track of 802.3z auto-negotation state */ +/* variables as shown in Figure 37-6 of the IEEE 802.3z specification. */ +/******************************************************************************/ + +typedef struct +{ + /* Pointer to the operating system specific data structure. */ + void *pContext; + + /* Current auto-negotiation state. */ + unsigned long State; + #define AN_STATE_UNKNOWN 0 + #define AN_STATE_AN_ENABLE 1 + #define AN_STATE_AN_RESTART_INIT 2 + #define AN_STATE_AN_RESTART 3 + #define AN_STATE_DISABLE_LINK_OK 4 + #define AN_STATE_ABILITY_DETECT_INIT 5 + #define AN_STATE_ABILITY_DETECT 6 + #define AN_STATE_ACK_DETECT_INIT 7 + #define AN_STATE_ACK_DETECT 8 + #define AN_STATE_COMPLETE_ACK_INIT 9 + #define AN_STATE_COMPLETE_ACK 10 + #define AN_STATE_IDLE_DETECT_INIT 11 + #define AN_STATE_IDLE_DETECT 12 + #define AN_STATE_LINK_OK 13 + #define AN_STATE_NEXT_PAGE_WAIT_INIT 14 + #define AN_STATE_NEXT_PAGE_WAIT 16 + + /* Link timer. */ + unsigned long LinkTime_us; + + /* Current time. */ + unsigned long CurrentTime_us; + + /* Ability, idle, and ack match functions. */ + unsigned long AbilityMatchCnt; + + /* Need these values for consistency check. */ + unsigned short AbilityMatchCfg; + + unsigned short reserved; + + char AbilityMatch; + char IdleMatch; + char AckMatch; + char reserved1; + + /* Tx config data */ + union + { + /* The TxConfig register is arranged as follows: */ + /* */ + /* MSB LSB */ + /* +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ + /* | D7| D6| D5| D4| D3| D2| D1| D0|D15|D14|D13|D12|D11|D10| D9| D8| */ + /* +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ + struct + { +#ifdef BIG_ENDIAN_HOST + unsigned short D7:1; /* PS1 */ + unsigned short D6:1; /* HD */ + unsigned short D5:1; /* FD */ + unsigned short D4:1; + unsigned short D3:1; + unsigned short D2:1; + unsigned short D1:1; + unsigned short D0:1; + unsigned short D15:1; /* NP */ + unsigned short D14:1; /* ACK */ + unsigned short D13:1; /* RF2 */ + unsigned short D12:1; /* RF1 */ + unsigned short D11:1; + unsigned short D10:1; + unsigned short D9:1; + unsigned short D8:1; /* PS2 */ +#else /* BIG_ENDIAN_HOST */ + unsigned int D8:1; /* PS2 */ + unsigned int D9:1; + unsigned int D10:1; + unsigned int D11:1; + unsigned int D12:1; /* RF1 */ + unsigned int D13:1; /* RF2 */ + unsigned int D14:1; /* ACK */ + unsigned int D15:1; /* NP */ + unsigned int D0:1; + unsigned int D1:1; + unsigned int D2:1; + unsigned int D3:1; + unsigned int D4:1; + unsigned int D5:1; /* FD */ + unsigned int D6:1; /* HD */ + unsigned int D7:1; /* PS1 */ +#endif + } bits; + + unsigned short AsUSHORT; + + #define D8_PS2 bits.D8 + #define D12_RF1 bits.D12 + #define D13_RF2 bits.D13 + #define D14_ACK bits.D14 + #define D15_NP bits.D15 + #define D5_FD bits.D5 + #define D6_HD bits.D6 + #define D7_PS1 bits.D7 + } TxConfig; + + /* Rx config data */ + union + { + /* The RxConfig register is arranged as follows: */ + /* */ + /* MSB LSB */ + /* +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ + /* | D7| D6| D5| D4| D3| D2| D1| D0|D15|D14|D13|D12|D11|D10| D9| D8| */ + /* +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ + struct + { +#ifdef BIG_ENDIAN_HOST + unsigned short D7:1; /* PS1 */ + unsigned short D6:1; /* HD */ + unsigned short D5:1; /* FD */ + unsigned short D4:1; + unsigned short D3:1; + unsigned short D2:1; + unsigned short D1:1; + unsigned short D0:1; + unsigned short D15:1; /* NP */ + unsigned short D14:1; /* ACK */ + unsigned short D13:1; /* RF2 */ + unsigned short D12:1; /* RF1 */ + unsigned short D11:1; + unsigned short D10:1; + unsigned short D9:1; + unsigned short D8:1; /* PS2 */ +#else /* BIG_ENDIAN_HOST */ + unsigned int D8:1; /* PS2 */ + unsigned int D9:1; + unsigned int D10:1; + unsigned int D11:1; + unsigned int D12:1; /* RF1 */ + unsigned int D13:1; /* RF2 */ + unsigned int D14:1; /* ACK */ + unsigned int D15:1; /* NP */ + unsigned int D0:1; + unsigned int D1:1; + unsigned int D2:1; + unsigned int D3:1; + unsigned int D4:1; + unsigned int D5:1; /* FD */ + unsigned int D6:1; /* HD */ + unsigned int D7:1; /* PS1 */ +#endif + } bits; + + unsigned short AsUSHORT; + } RxConfig; + + #define AN_CONFIG_NP 0x0080 + #define AN_CONFIG_ACK 0x0040 + #define AN_CONFIG_RF2 0x0020 + #define AN_CONFIG_RF1 0x0010 + #define AN_CONFIG_PS2 0x0001 + #define AN_CONFIG_PS1 0x8000 + #define AN_CONFIG_HD 0x4000 + #define AN_CONFIG_FD 0x2000 + + + /* Management registers. */ + + /* Control register. */ + union + { + struct + { + unsigned int an_enable:1; + unsigned int loopback:1; + unsigned int reset:1; + unsigned int restart_an:1; + } bits; + + unsigned short AsUSHORT; + + #define mr_an_enable Mr0.bits.an_enable + #define mr_loopback Mr0.bits.loopback + #define mr_main_reset Mr0.bits.reset + #define mr_restart_an Mr0.bits.restart_an + } Mr0; + + /* Status register. */ + union + { + struct + { + unsigned int an_complete:1; + unsigned int link_ok:1; + } bits; + + unsigned short AsUSHORT; + + #define mr_an_complete Mr1.bits.an_complete + #define mr_link_ok Mr1.bits.link_ok + } Mr1; + + /* Advertisement register. */ + union + { + struct + { + unsigned int reserved_4:5; + unsigned int full_duplex:1; + unsigned int half_duplex:1; + unsigned int sym_pause:1; + unsigned int asym_pause:1; + unsigned int reserved_11:3; + unsigned int remote_fault1:1; + unsigned int remote_fault2:1; + unsigned int reserved_14:1; + unsigned int next_page:1; + } bits; + + unsigned short AsUSHORT; + + #define mr_adv_full_duplex Mr4.bits.full_duplex + #define mr_adv_half_duplex Mr4.bits.half_duplex + #define mr_adv_sym_pause Mr4.bits.sym_pause + #define mr_adv_asym_pause Mr4.bits.asym_pause + #define mr_adv_remote_fault1 Mr4.bits.remote_fault1 + #define mr_adv_remote_fault2 Mr4.bits.remote_fault2 + #define mr_adv_next_page Mr4.bits.next_page + } Mr4; + + /* Link partner advertisement register. */ + union + { + struct + { + unsigned int reserved_4:5; + unsigned int lp_full_duplex:1; + unsigned int lp_half_duplex:1; + unsigned int lp_sym_pause:1; + unsigned int lp_asym_pause:1; + unsigned int reserved_11:3; + unsigned int lp_remote_fault1:1; + unsigned int lp_remote_fault2:1; + unsigned int lp_ack:1; + unsigned int lp_next_page:1; + } bits; + + unsigned short AsUSHORT; + + #define mr_lp_adv_full_duplex Mr5.bits.lp_full_duplex + #define mr_lp_adv_half_duplex Mr5.bits.lp_half_duplex + #define mr_lp_adv_sym_pause Mr5.bits.lp_sym_pause + #define mr_lp_adv_asym_pause Mr5.bits.lp_asym_pause + #define mr_lp_adv_remote_fault1 Mr5.bits.lp_remote_fault1 + #define mr_lp_adv_remote_fault2 Mr5.bits.lp_remote_fault2 + #define mr_lp_adv_next_page Mr5.bits.lp_next_page + } Mr5; + + /* Auto-negotiation expansion register. */ + union + { + struct + { + unsigned int reserved_0:1; + unsigned int page_received:1; + unsigned int next_pageable:1; + unsigned int reserved_15:13; + } bits; + + unsigned short AsUSHORT; + } Mr6; + + /* Auto-negotiation next page transmit register. */ + union + { + struct + { + unsigned int code_field:11; + unsigned int toggle:1; + unsigned int ack2:1; + unsigned int message_page:1; + unsigned int reserved_14:1; + unsigned int next_page:1; + } bits; + + unsigned short AsUSHORT; + + #define mr_np_tx Mr7.AsUSHORT + } Mr7; + + /* Auto-negotiation link partner ability register. */ + union + { + struct + { + unsigned int code_field:11; + unsigned int toggle:1; + unsigned int ack2:1; + unsigned int message_page:1; + unsigned int ack:1; + unsigned int next_page:1; + } bits; + + unsigned short AsUSHORT; + + #define mr_lp_np_rx Mr8.AsUSHORT + } Mr8; + + /* Extended status register. */ + union + { + struct + { + unsigned int reserved_11:12; + unsigned int base1000_t_hd:1; + unsigned int base1000_t_fd:1; + unsigned int base1000_x_hd:1; + unsigned int base1000_x_fd:1; + } bits; + + unsigned short AsUSHORT; + } Mr15; + + /* Miscellaneous state variables. */ + union + { + struct + { + unsigned int toggle_tx:1; + unsigned int toggle_rx:1; + unsigned int np_rx:1; + unsigned int page_rx:1; + unsigned int np_loaded:1; + } bits; + + unsigned short AsUSHORT; + + #define mr_toggle_tx MrMisc.bits.toggle_tx + #define mr_toggle_rx MrMisc.bits.toggle_rx + #define mr_np_rx MrMisc.bits.np_rx + #define mr_page_rx MrMisc.bits.page_rx + #define mr_np_loaded MrMisc.bits.np_loaded + } MrMisc; + +} AN_STATE_INFO, *PAN_STATE_INFO; + + + +/******************************************************************************/ +/* Return code of Autoneg8023z. */ +/******************************************************************************/ + +typedef enum +{ + AUTONEG_STATUS_OK = 0, + AUTONEG_STATUS_DONE = 1, + AUTONEG_STATUS_TIMER_ENABLED = 2, +// AUTONEG_STATUS_FAILED = 0xffffffff, + AUTONEG_STATUS_FAILED = 0xfffffff +} AUTONEG_STATUS, *PAUTONEG_STATUS; + + + +/******************************************************************************/ +/* Function prototypes. */ +/******************************************************************************/ + +AUTONEG_STATUS Autoneg8023z(PAN_STATE_INFO pAnInfo); +void AutonegInit(PAN_STATE_INFO pAnInfo); + + + +/******************************************************************************/ +/* The following functions are defined in the os-dependent module. */ +/******************************************************************************/ + +void MM_AnTxConfig(PAN_STATE_INFO pAnInfo); +void MM_AnTxIdle(PAN_STATE_INFO pAnInfo); +char MM_AnRxConfig(PAN_STATE_INFO pAnInfo, unsigned short *pRxConfig); + + + +#endif /* AUTONEG_H */ + diff -u --recursive --new-file linux-2.4.26/drivers/net/bcm/b57diag.c linux-2.4.26.patch/drivers/net/bcm/b57diag.c --- linux-2.4.26/drivers/net/bcm/b57diag.c 1969-12-31 16:00:00.000000000 -0800 +++ linux-2.4.26.patch/drivers/net/bcm/b57diag.c 2004-06-22 16:07:37.000000000 -0700 @@ -0,0 +1,706 @@ +/******************************************************************************/ +/* */ +/* Broadcom BCM5700 Linux Network Driver, Copyright (c) 2000 - 2004 Broadcom */ +/* Corporation. */ +/* All rights reserved. */ +/* */ +/* This program is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU General Public License as published by */ +/* the Free Software Foundation, located in the file LICENSE. */ +/* */ +/* ethtool -t selftest code. */ +/* */ +/******************************************************************************/ + +#include "mm.h" +#ifdef ETHTOOL_TEST + +typedef struct reg_entry +{ + LM_UINT16 offset; + LM_UINT16 flags; +#define BCM5705_ONLY 1 +#define NOT_FOR_BCM5705 2 +#define NOT_FOR_BCM5788 4 + LM_UINT32 read_mask; + LM_UINT32 write_mask; +} reg_entry_t; + +typedef struct mem_entry +{ + LM_UINT32 offset; + LM_UINT32 len; +} mem_entry_t; + +/* Returns 1 on success, 0 on failure */ +int +b57_test_registers(UM_DEVICE_BLOCK *pUmDevice) +{ + LM_DEVICE_BLOCK *pDevice = &pUmDevice->lm_dev; + int ret; + int i, bcm5705; + LM_UINT32 offset, read_mask, write_mask, val, save_val, read_val; + static reg_entry_t reg_tbl[] = { + /* MAC block */ + { 0x0400, 0x0002, 0x00000000, 0x00ef6f8c }, + { 0x0400, 0x0001, 0x00000000, 0x01ef6b8c }, /* 5705 */ + { 0x0404, 0x0002, 0x03800107, 0x00000000 }, + { 0x0404, 0x0001, 0x03800100, 0x00000000 }, /* 5705 */ + { 0x0408, 0x0002, 0x00000000, 0x07c01400 }, + { 0x0408, 0x0001, 0x00000000, 0x07c01000 }, /* 5705 */ + { 0x040c, 0x0000, 0x00000000, 0xfff8007f }, + { 0x0410, 0x0000, 0x00000000, 0x0000ffff }, + { 0x0414, 0x0000, 0x00000000, 0xffffffff }, + { 0x0418, 0x0000, 0x00000000, 0x0000ffff }, + { 0x041c, 0x0000, 0x00000000, 0xffffffff }, + { 0x0420, 0x0000, 0x00000000, 0x0000ffff }, + { 0x0424, 0x0000, 0x00000000, 0xffffffff }, + { 0x0428, 0x0000, 0x00000000, 0x0000ffff }, + { 0x042c, 0x0000, 0x00000000, 0xffffffff }, + { 0x0430, 0x0002, 0x00000000, 0xffffffff }, + { 0x0430, 0x0001, 0x00000000, 0x0fff03ff }, /* 5705 */ + { 0x0434, 0x0002, 0x00000000, 0x0fffffff }, + { 0x0434, 0x0001, 0x00000000, 0x000001ff }, /* 5705 */ + { 0x043c, 0x0000, 0x00000000, 0x0000ffff }, + { 0x0454, 0x0000, 0x00000000, 0x00000010 }, + { 0x045c, 0x0000, 0x00000000, 0x00000070 }, + { 0x0464, 0x0000, 0x00000000, 0x00003fff }, + { 0x0468, 0x0002, 0x00000000, 0x000007fc }, + { 0x0468, 0x0001, 0x00000000, 0x000007dc }, /* 5705 */ + { 0x0470, 0x0000, 0x00000000, 0xffffffff }, + { 0x0474, 0x0000, 0x00000000, 0xffffffff }, + { 0x0478, 0x0000, 0x00000000, 0xffffffff }, + { 0x047c, 0x0000, 0x00000000, 0xffffffff }, + { 0x0480, 0x0002, 0x00000000, 0xffffffff }, + { 0x0480, 0x0001, 0x00000000, 0xe7ffffff }, /* 5705 */ + { 0x0484, 0x0000, 0x00000000, 0xffffffff }, + { 0x0488, 0x0002, 0x00000000, 0xffffffff }, + { 0x0488, 0x0001, 0x00000000, 0xe7ffffff }, /* 5705 */ + { 0x048c, 0x0000, 0x00000000, 0xffffffff }, + { 0x0490, 0x0002, 0x00000000, 0xffffffff }, + { 0x0490, 0x0001, 0x00000000, 0xe7ffffff }, /* 5705 */ + { 0x0494, 0x0000, 0x00000000, 0xffffffff }, + { 0x0498, 0x0002, 0x00000000, 0xffffffff }, + { 0x0498, 0x0001, 0x00000000, 0xe7ffffff }, /* 5705 */ + { 0x049c, 0x0000, 0x00000000, 0xffffffff }, + { 0x04a0, 0x0002, 0x00000000, 0xffffffff }, + { 0x04a0, 0x0001, 0x00000000, 0xe7ffffff }, /* 5705 */ + { 0x04a4, 0x0000, 0x00000000, 0xffffffff }, + { 0x04a8, 0x0002, 0x00000000, 0xffffffff }, + { 0x04a8, 0x0001, 0x00000000, 0xe7ffffff }, /* 5705 */ + { 0x04ac, 0x0000, 0x00000000, 0xffffffff }, + { 0x04b0, 0x0002, 0x00000000, 0xffffffff }, + { 0x04b0, 0x0001, 0x00000000, 0xe7ffffff }, /* 5705 */ + { 0x04b4, 0x0000, 0x00000000, 0xffffffff }, + { 0x04b8, 0x0002, 0x00000000, 0xffffffff }, + { 0x04b8, 0x0001, 0x00000000, 0xe7ffffff }, /* 5705 */ + { 0x04bc, 0x0000, 0x00000000, 0xffffffff }, + { 0x04c0, 0x0002, 0x00000000, 0xffffffff }, + { 0x04c4, 0x0002, 0x00000000, 0xffffffff }, + { 0x04c8, 0x0002, 0x00000000, 0xffffffff }, + { 0x04cc, 0x0002, 0x00000000, 0xffffffff }, + { 0x04d0, 0x0002, 0x00000000, 0xffffffff }, + { 0x04d4, 0x0002, 0x00000000, 0xffffffff }, + { 0x04d8, 0x0002, 0x00000000, 0xffffffff }, + { 0x04dc, 0x0002, 0x00000000, 0xffffffff }, + { 0x04e0, 0x0002, 0x00000000, 0xffffffff }, + { 0x04e4, 0x0002, 0x00000000, 0xffffffff }, + { 0x04e8, 0x0002, 0x00000000, 0xffffffff }, + { 0x04ec, 0x0002, 0x00000000, 0xffffffff }, + { 0x04f0, 0x0002, 0x00000000, 0xffffffff }, + { 0x04f4, 0x0002, 0x00000000, 0xffffffff }, + { 0x04f8, 0x0002, 0x00000000, 0xffffffff }, + { 0x04fc, 0x0002, 0x00000000, 0xffffffff }, + { 0x0500, 0x0002, 0x00000000, 0x000000f8 }, + { 0x0500, 0x0001, 0x00000000, 0x00000008 }, /* 5705 */ + + /* Send Data Initiator Control Registers */ + { 0x0c00, 0x0000, 0x00000000, 0x00000006 }, + { 0x0c04, 0x0000, 0x00000004, 0x00000000 }, + { 0x0c08, 0x0000, 0x00000000, 0x0000001b }, + { 0x0c0c, 0x0002, 0x00000000, 0x00ffffff }, + { 0x0c0c, 0x0001, 0x00000000, 0x00000001 }, + { 0x0c80, 0x0000, 0x000003ff, 0x00000000 }, + { 0x0c84, 0x0002, 0x000003ff, 0x00000000 }, + { 0x0c88, 0x0002, 0x000003ff, 0x00000000 }, + { 0x0c8c, 0x0002, 0x000003ff, 0x00000000 }, + { 0x0c90, 0x0002, 0x000003ff, 0x00000000 }, + { 0x0c94, 0x0002, 0x000003ff, 0x00000000 }, + { 0x0c98, 0x0002, 0x000003ff, 0x00000000 }, + { 0x0c9c, 0x0002, 0x000003ff, 0x00000000 }, + { 0x0ca0, 0x0002, 0x000003ff, 0x00000000 }, + { 0x0ca4, 0x0002, 0x000003ff, 0x00000000 }, + { 0x0ca8, 0x0002, 0x000003ff, 0x00000000 }, + { 0x0cac, 0x0002, 0x000003ff, 0x00000000 }, + { 0x0cb0, 0x0002, 0x000003ff, 0x00000000 }, + { 0x0cb4, 0x0002, 0x000003ff, 0x00000000 }, + { 0x0cb8, 0x0002, 0x000003ff, 0x00000000 }, + { 0x0cbc, 0x0002, 0x000003ff, 0x00000000 }, + { 0x0cc0, 0x0002, 0x000003ff, 0x00000000 }, + { 0x0cc4, 0x0002, 0x000003ff, 0x00000000 }, + { 0x0cc8, 0x0002, 0x000003ff, 0x00000000 }, + { 0x0ccc, 0x0002, 0x000003ff, 0x00000000 }, + { 0x0cd0, 0x0002, 0x000003ff, 0x00000000 }, + { 0x0cd4, 0x0002, 0x000003ff, 0x00000000 }, + { 0x0cd8, 0x0002, 0x000003ff, 0x00000000 }, + { 0x0cdc, 0x0002, 0x000003ff, 0x00000000 }, + { 0x0ce0, 0x0001, 0x00000000, 0xffffffff }, /* 5705 */ + { 0x0ce4, 0x0001, 0x00000000, 0xffffffff }, /* 5705 */ + { 0x0ce8, 0x0001, 0x00000000, 0x00ffffff }, /* 5705 */ + { 0x0cec, 0x0001, 0x00000000, 0x000efcf7 }, /* 5705 */ + { 0x0cf0, 0x0001, 0x00000000, 0x0000ffff }, /* 5705 */ + { 0x0cf4, 0x0001, 0x00000000, 0x20000000 }, /* 5705 */ + + /* SDC Control Registers */ + { 0x1000, 0x0000, 0x00000000, 0x00000002 }, + { 0x1008, 0x0001, 0x00000000, 0x40000000 }, /* 5705 */ + + /* Send BD Ring Selector Control Registers. */ + { 0x1400, 0x0000, 0x00000000, 0x00000006 }, + { 0x1404, 0x0000, 0x00000004, 0x00000000 }, + { 0x1408, 0x0000, 0x0000ffff, 0x00000000 }, + { 0x1440, 0x0000, 0x0000000f, 0x00000000 }, + { 0x1444, 0x0002, 0x0000000f, 0x00000000 }, + { 0x1448, 0x0002, 0x0000000f, 0x00000000 }, + { 0x144c, 0x0002, 0x0000000f, 0x00000000 }, + { 0x1450, 0x0002, 0x0000000f, 0x00000000 }, + { 0x1454, 0x0002, 0x0000000f, 0x00000000 }, + { 0x1458, 0x0002, 0x0000000f, 0x00000000 }, + { 0x145c, 0x0002, 0x0000000f, 0x00000000 }, + { 0x1460, 0x0002, 0x0000000f, 0x00000000 }, + { 0x1464, 0x0002, 0x0000000f, 0x00000000 }, + { 0x1468, 0x0002, 0x0000000f, 0x00000000 }, + { 0x146c, 0x0002, 0x0000000f, 0x00000000 }, + { 0x1470, 0x0002, 0x0000000f, 0x00000000 }, + { 0x1474, 0x0002, 0x0000000f, 0x00000000 }, + { 0x1478, 0x0002, 0x0000000f, 0x00000000 }, + { 0x147c, 0x0002, 0x0000000f, 0x00000000 }, + + /* Send BD Inititor Control Registers.*/ + { 0x1800, 0x0000, 0x00000000, 0x00000006 }, + { 0x1804, 0x0000, 0x00000004, 0x00000000 }, + { 0x1808, 0x0000, 0xffffffff, 0x00000000 }, + { 0x180c, 0x0002, 0xffffffff, 0x00000000 }, + { 0x1810, 0x0002, 0xffffffff, 0x00000000 }, + { 0x1814, 0x0002, 0xffffffff, 0x00000000 }, + { 0x1818, 0x0002, 0xffffffff, 0x00000000 }, + { 0x181c, 0x0002, 0xffffffff, 0x00000000 }, + { 0x1820, 0x0002, 0xffffffff, 0x00000000 }, + { 0x1824, 0x0002, 0xffffffff, 0x00000000 }, + { 0x1828, 0x0002, 0xffffffff, 0x00000000 }, + { 0x182c, 0x0002, 0xffffffff, 0x00000000 }, + { 0x1830, 0x0002, 0xffffffff, 0x00000000 }, + { 0x1834, 0x0002, 0xffffffff, 0x00000000 }, + { 0x1838, 0x0002, 0xffffffff, 0x00000000 }, + { 0x183c, 0x0002, 0xffffffff, 0x00000000 }, + { 0x1840, 0x0002, 0xffffffff, 0x00000000 }, + { 0x1844, 0x0002, 0xffffffff, 0x00000000 }, + + /* Send BD Completion Control Registers */ + { 0x1c00, 0x0000, 0x00000000, 0x00000002 }, + + /* Receive List Placement Control Registers. */ + { 0x2000, 0x0000, 0x00000000, 0x0000001e }, + { 0x2004, 0x0000, 0x0000001c, 0x00000000 }, + { 0x2010, 0x0002, 0x00000000, 0x00007fff }, + { 0x2010, 0x0001, 0x00000000, 0x000060ff }, /* 5705 */ + { 0x2014, 0x0000, 0x00000000, 0x00000001 }, + { 0x2200, 0x0000, 0x000003ff, 0x00000000 }, + { 0x2204, 0x0002, 0x000003ff, 0x00000000 }, + { 0x2208, 0x0002, 0x000003ff, 0x00000000 }, + { 0x220c, 0x0002, 0x000003ff, 0x00000000 }, + { 0x2210, 0x0002, 0x000003ff, 0x00000000 }, + { 0x2214, 0x0002, 0x000003ff, 0x00000000 }, + { 0x2218, 0x0002, 0x000003ff, 0x00000000 }, + { 0x221c, 0x0002, 0x000003ff, 0x00000000 }, + { 0x2220, 0x0002, 0x000003ff, 0x00000000 }, + { 0x2224, 0x0002, 0x000003ff, 0x00000000 }, + { 0x2228, 0x0002, 0x000003ff, 0x00000000 }, + { 0x222c, 0x0002, 0x000003ff, 0x00000000 }, + { 0x2230, 0x0002, 0x000003ff, 0x00000000 }, + { 0x2234, 0x0002, 0x000003ff, 0x00000000 }, + { 0x2238, 0x0002, 0x000003ff, 0x00000000 }, + { 0x223c, 0x0002, 0x000003ff, 0x00000000 }, + { 0x2240, 0x0002, 0x000003ff, 0x00000000 }, + { 0x2244, 0x0002, 0x000003ff, 0x00000000 }, + { 0x2248, 0x0002, 0x000003ff, 0x00000000 }, + { 0x224c, 0x0000, 0x000003ff, 0x00000000 }, + { 0x2250, 0x0000, 0x000003ff, 0x00000000 }, + { 0x2254, 0x0000, 0x000003ff, 0x00000000 }, + { 0x2258, 0x0002, 0x000003ff, 0x00000000 }, + + /* Receive Data and Receive BD Initiator Control Registers. */ + { 0x2400, 0x0002, 0x00000000, 0x0000001e }, + { 0x2400, 0x0001, 0x00000000, 0x0000001a }, /* 5705 */ + { 0x2404, 0x0000, 0x0000001c, 0x00000000 }, + { 0x2408, 0x0002, 0x00000000, 0x0000ffff }, + { 0x2440, 0x0002, 0x00000000, 0xffffffff }, + { 0x2444, 0x0002, 0x00000000, 0xffffffff }, + { 0x2448, 0x0002, 0x00000000, 0x00000003 }, + { 0x244c, 0x0002, 0x00000000, 0xffffffff }, + { 0x2450, 0x0000, 0x00000000, 0xffffffff }, + { 0x2454, 0x0000, 0x00000000, 0xffffffff }, + { 0x2458, 0x0000, 0x00000000, 0xffff0002 }, + { 0x245c, 0x0000, 0x00000000, 0xffffffff }, + { 0x2470, 0x0002, 0xffffffff, 0x00000000 }, + { 0x2474, 0x0000, 0xffffffff, 0x00000000 }, + { 0x2478, 0x0002, 0xffffffff, 0x00000000 }, + { 0x2480, 0x0000, 0xffffffff, 0x00000000 }, + { 0x2484, 0x0002, 0xffffffff, 0x00000000 }, + { 0x2488, 0x0002, 0xffffffff, 0x00000000 }, + { 0x248c, 0x0002, 0xffffffff, 0x00000000 }, + { 0x2490, 0x0002, 0xffffffff, 0x00000000 }, + { 0x2494, 0x0002, 0xffffffff, 0x00000000 }, + { 0x2498, 0x0002, 0xffffffff, 0x00000000 }, + { 0x249c, 0x0002, 0xffffffff, 0x00000000 }, + { 0x24a0, 0x0002, 0xffffffff, 0x00000000 }, + { 0x24a4, 0x0002, 0xffffffff, 0x00000000 }, + { 0x24a8, 0x0002, 0xffffffff, 0x00000000 }, + { 0x24ac, 0x0002, 0xffffffff, 0x00000000 }, + { 0x24b0, 0x0002, 0xffffffff, 0x00000000 }, + { 0x24b4, 0x0002, 0xffffffff, 0x00000000 }, + { 0x24b8, 0x0002, 0xffffffff, 0x00000000 }, + { 0x24bc, 0x0002, 0xffffffff, 0x00000000 }, + { 0x24c0, 0x0000, 0xffffffff, 0x00000000 }, + + /* Receive Data Completion Control Registers */ + { 0x2800, 0x0000, 0x00000000, 0x00000002 }, + + /* Receive BD Initiator Control Registers. */ + { 0x2c00, 0x0000, 0x00000000, 0x00000006 }, + { 0x2c04, 0x0000, 0x00000004, 0x00000000 }, + { 0x2c18, 0x0002, 0x00000000, 0xffffffff }, + { 0x2c18, 0x0001, 0x00000000, 0x000003ff }, /* 5705 */ + { 0x2c1c, 0x0002, 0x00000000, 0xffffffff }, + + /* Receive BD Completion Control Registers. */ + { 0x3000, 0x0000, 0x00000000, 0x00000006 }, + { 0x3004, 0x0000, 0x00000004, 0x00000000 }, + { 0x3008, 0x0002, 0x00000000, 0x000000ff }, + { 0x300c, 0x0000, 0x00000000, 0x000001ff }, + + /* Host Coalescing Control Registers. */ + { 0x3c00, 0x0002, 0x00000000, 0x00000004 }, + { 0x3c00, 0x0001, 0x00000000, 0x000000f6 }, /* 5705 */ + { 0x3c04, 0x0000, 0x00000004, 0x00000000 }, + { 0x3c08, 0x0002, 0x00000000, 0xffffffff }, + { 0x3c08, 0x0001, 0x00000000, 0x000003ff }, /* 5705 */ + { 0x3c0c, 0x0002, 0x00000000, 0xffffffff }, + { 0x3c0c, 0x0001, 0x00000000, 0x000003ff }, /* 5705 */ + { 0x3c10, 0x0002, 0x00000000, 0xffffffff }, + { 0x3c10, 0x0005, 0x00000000, 0x000000ff }, /* 5705 */ + { 0x3c14, 0x0002, 0x00000000, 0xffffffff }, + { 0x3c14, 0x0005, 0x00000000, 0x000000ff }, /* 5705 */ + { 0x3c18, 0x0002, 0x00000000, 0xffffffff }, + { 0x3c1c, 0x0002, 0x00000000, 0xffffffff }, + { 0x3c20, 0x0002, 0x00000000, 0xffffffff }, + { 0x3c20, 0x0005, 0x00000000, 0x000000ff }, /* 5705 */ + { 0x3c24, 0x0002, 0x00000000, 0xffffffff }, + { 0x3c24, 0x0005, 0x00000000, 0x000000ff }, /* 5705 */ + { 0x3c28, 0x0002, 0x00000000, 0xffffffff }, + { 0x3c30, 0x0002, 0x00000000, 0xffffffff }, + { 0x3c34, 0x0002, 0x00000000, 0xffffffff }, + { 0x3c38, 0x0000, 0x00000000, 0xffffffff }, + { 0x3c3c, 0x0000, 0x00000000, 0xffffffff }, + { 0x3c40, 0x0000, 0xffffffff, 0x00000000 }, + { 0x3c44, 0x0000, 0xffffffff, 0x00000000 }, + { 0x3c50, 0x0002, 0x00000000, 0x000000ff }, + { 0x3c54, 0x0000, 0x00000000, 0x000000ff }, + { 0x3c80, 0x0002, 0x00000000, 0x000007ff }, + { 0x3c80, 0x0001, 0x00000000, 0x000001ff }, /* 5705 */ + { 0x3c84, 0x0002, 0x00000000, 0x000007ff }, + { 0x3c88, 0x0002, 0x00000000, 0x000007ff }, + { 0x3c8c, 0x0002, 0x00000000, 0x000007ff }, + { 0x3c90, 0x0002, 0x00000000, 0x000007ff }, + { 0x3c94, 0x0002, 0x00000000, 0x000007ff }, + { 0x3c98, 0x0002, 0x00000000, 0x000007ff }, + { 0x3c9c, 0x0002, 0x00000000, 0x000007ff }, + { 0x3ca0, 0x0002, 0x00000000, 0x000007ff }, + { 0x3ca4, 0x0002, 0x00000000, 0x000007ff }, + { 0x3ca8, 0x0002, 0x00000000, 0x000007ff }, + { 0x3cac, 0x0002, 0x00000000, 0x000007ff }, + { 0x3cb0, 0x0002, 0x00000000, 0x000007ff }, + { 0x3cb4, 0x0002, 0x00000000, 0x000007ff }, + { 0x3cb8, 0x0002, 0x00000000, 0x000007ff }, + { 0x3cbc, 0x0002, 0x00000000, 0x000007ff }, + { 0x3cc0, 0x0000, 0x00000000, 0x000001ff }, + { 0x3cc4, 0x0002, 0x00000000, 0x000001ff }, + { 0x3cc8, 0x0002, 0x00000000, 0x000001ff }, + { 0x3ccc, 0x0002, 0x00000000, 0x000001ff }, + { 0x3cd0, 0x0002, 0x00000000, 0x000001ff }, + { 0x3cd4, 0x0002, 0x00000000, 0x000001ff }, + { 0x3cd8, 0x0002, 0x00000000, 0x000001ff }, + { 0x3cdc, 0x0002, 0x00000000, 0x000001ff }, + { 0x3ce0, 0x0002, 0x00000000, 0x000001ff }, + { 0x3ce4, 0x0002, 0x00000000, 0x000001ff }, + { 0x3ce8, 0x0002, 0x00000000, 0x000001ff }, + { 0x3cec, 0x0002, 0x00000000, 0x000001ff }, + { 0x3cf0, 0x0002, 0x00000000, 0x000001ff }, + { 0x3cf4, 0x0002, 0x00000000, 0x000001ff }, + { 0x3cf8, 0x0002, 0x00000000, 0x000001ff }, + { 0x3cfc, 0x0002, 0x00000000, 0x000001ff }, + + /* Memory Arbiter Registers */ + { 0x4000, 0x0002, 0x00000000, 0x001ffffe }, + { 0x4000, 0x0001, 0x00000000, 0x38111e7e }, + { 0x4004, 0x0002, 0x001ffffc, 0x00000000 }, + { 0x4004, 0x0002, 0x00111dfc, 0x00000000 }, + { 0x4008, 0x0000, 0x00000000, 0x001fffff }, + { 0x400c, 0x0000, 0x00000000, 0x001fffff }, + + /* Buffer Manager Control Registers. */ + { 0x4400, 0x0000, 0x00000000, 0x0000001c }, + { 0x4404, 0x0000, 0x00000014, 0x00000000 }, + { 0x4408, 0x0000, 0x00000000, 0x007fff80 }, + { 0x440c, 0x0000, 0x00000000, 0x007fffff }, + { 0x4410, 0x0000, 0x00000000, 0x0000003f }, + { 0x4414, 0x0000, 0x00000000, 0x000001ff }, + { 0x4418, 0x0000, 0x00000000, 0x000001ff }, + { 0x4420, 0x0000, 0xffffffff, 0x00000000 }, + { 0x4428, 0x0002, 0xffffffff, 0x00000000 }, + { 0x442c, 0x0002, 0xffffffff, 0x00000000 }, + { 0x4430, 0x0002, 0xffffffff, 0x00000000 }, + { 0x4440, 0x0002, 0xffffffff, 0x00000000 }, + { 0x4448, 0x0002, 0xffffffff, 0x00000000 }, + { 0x444c, 0x0000, 0xffffffff, 0x00000000 }, + { 0x4450, 0x0000, 0xffffffff, 0x00000000 }, + { 0x4454, 0x0000, 0xffffffff, 0x00000000 }, + { 0x4458, 0x0001, 0x00000000, 0x000001ff }, /* 5705 */ + + { 0x4800, 0x0002, 0x00000000, 0x000003fe }, + { 0x4800, 0x0001, 0x00000000, 0xc00003fe }, /* 5705 */ + { 0x4804, 0x0000, 0x000003fc, 0x00000000 }, + { 0x4c00, 0x0002, 0x00000000, 0x000003fc }, + { 0x4c00, 0x0001, 0x00000000, 0x000007fc }, /* 5705 */ + { 0x4c04, 0x0000, 0x000003fc, 0x00000000 }, + + /* Mailbox Registers */ + { 0x5804, 0x0000, 0x00000000, 0xffffffff }, + { 0x586c, 0x0000, 0x00000000, 0x000001ff }, + { 0x5874, 0x0002, 0x00000000, 0x000001ff }, + { 0x5884, 0x0000, 0x00000000, 0x000007ff }, + { 0x5904, 0x0000, 0x00000000, 0x000001ff }, + { 0x5984, 0x0002, 0x00000000, 0x000001ff }, + { 0x5a04, 0x0000, 0x00000000, 0xffffffff }, + { 0x5a0c, 0x0000, 0x00000000, 0xffffffff }, + + /* Flow Through Queues. */ + { 0x5c14, 0x0002, 0xffffffff, 0x00000000 }, + { 0x5c24, 0x0002, 0xffffffff, 0x00000000 }, + { 0x5c34, 0x0002, 0xffffffff, 0x00000000 }, + { 0x5c44, 0x0002, 0xffffffff, 0x00000000 }, + { 0x5c54, 0x0002, 0xffffffff, 0x00000000 }, + { 0x5c64, 0x0002, 0xffffffff, 0x00000000 }, + { 0x5c74, 0x0002, 0xffffffff, 0x00000000 }, + { 0x5c84, 0x0002, 0xffffffff, 0x00000000 }, + { 0x5c94, 0x0002, 0xffffffff, 0x00000000 }, + { 0x5ca4, 0x0002, 0xffffffff, 0x00000000 }, + { 0x5cb4, 0x0002, 0xffffffff, 0x00000000 }, + { 0x5cc4, 0x0002, 0xffffffff, 0x00000000 }, + { 0x5cd4, 0x0002, 0xffffffff, 0x00000000 }, + { 0x5ce4, 0x0002, 0xffffffff, 0x00000000 }, + { 0x5cf4, 0x0002, 0xffffffff, 0x00000000 }, + { 0x5d04, 0x0002, 0xffffffff, 0x00000000 }, + { 0x5d14, 0x0002, 0xffffffff, 0x00000000 }, + { 0xffff, 0x0000, 0x00000000, 0x00000000 }, + }; + + if (T3_ASIC_5705_OR_5750(pDevice->ChipRevId)) { + bcm5705 = 1; + } + else { + bcm5705 = 0; + } + + ret = 1; + for (i = 0; reg_tbl[i].offset != 0xffff; i++) { + if (bcm5705 && (reg_tbl[i].flags & NOT_FOR_BCM5705)) + continue; + if (!bcm5705 && (reg_tbl[i].flags & BCM5705_ONLY)) + continue; + if ((pDevice->Flags & BCM5788_FLAG) && + (reg_tbl[i].flags & NOT_FOR_BCM5788)) + continue; + offset = (LM_UINT32) reg_tbl[i].offset; + read_mask = reg_tbl[i].read_mask; + write_mask = reg_tbl[i].write_mask; + + /* Save the original register content */ + save_val = LM_RegRd(pDevice, offset); + + /* Determine the read-only value. */ + read_val = save_val & read_mask; + + /* Write zero to the register, then make sure the read-only bits + are not changed and the read/write bits are all zeros. */ + LM_RegWr(pDevice, offset, 0, FALSE); + + val = LM_RegRd(pDevice, offset); + + /* Test the read-only and read/write bits. */ + if (((val & read_mask) != read_val) || + (val & write_mask)) { + + ret = 0; + LM_RegWr(pDevice, offset, save_val, FALSE); + break; + } + + + /* Write ones to all the bits defined by RdMask and WrMask, then + make sure the read-only bits are not changed and the + read/write bits are all ones. */ + LM_RegWr(pDevice, offset, read_mask | write_mask, FALSE); + + val = LM_RegRd(pDevice, offset); + + /* Test the read-only bits. */ + if ((val & read_mask) != read_val) { + ret = 0; + LM_RegWr(pDevice, offset, save_val, FALSE); + break; + } + + /* Test the read/write bits. */ + if ((val & write_mask) != write_mask) { + ret = 0; + LM_RegWr(pDevice, offset, save_val, FALSE); + break; + } + + LM_RegWr(pDevice, offset, save_val, FALSE); + } + + return ret; +} + + +/* Returns 1 on success, 0 on failure */ +int +b57_do_memory_test(LM_DEVICE_BLOCK *pDevice, LM_UINT32 start, LM_UINT32 size) +{ + const LM_UINT32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555, + 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa }; + LM_UINT32 offset; + int i; + + for (i = 0; i < sizeof(test_pattern)/sizeof(LM_UINT32); i++) { + for (offset = 0; offset < size; offset += 4) { + + LM_MemWrInd(pDevice, start + offset, test_pattern[i]); + + if (LM_MemRdInd(pDevice, start + offset) != + test_pattern[i]) { + return 0; + } + } + } + return 1; +} + +/* Returns 1 on success, 0 on failure */ +int +b57_test_memory(UM_DEVICE_BLOCK *pUmDevice) +{ + LM_DEVICE_BLOCK *pDevice = &pUmDevice->lm_dev; + int ret = 0; + int i; + mem_entry_t *mem_tbl; + + static mem_entry_t mem_tbl_570x[] = { + { 0x00000000, 0x01000}, + { 0x00002000, 0x1c000}, + { 0xffffffff, 0x00000} + }; + static mem_entry_t mem_tbl_5705[] = { + { 0x00000100, 0x0000c}, + { 0x00000200, 0x00008}, + { 0x00000b50, 0x00400}, + { 0x00004000, 0x00800}, + { 0x00006000, 0x01000}, + { 0x00008000, 0x02000}, + { 0x00010000, 0x0e000}, + { 0xffffffff, 0x00000} + }; + + if (T3_ASIC_5705_OR_5750(pDevice->ChipRevId)) { + mem_tbl = mem_tbl_5705; + } + else { + mem_tbl = mem_tbl_570x; + } + for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) { + if ((ret = b57_do_memory_test(pDevice, mem_tbl[i].offset, + mem_tbl[i].len)) == 0) { + return ret; + } + } + + return ret; +} + +#define EEPROM_SIZE 0x100 + +/* Returns 1 on success, 0 on failure */ +int +b57_test_nvram(UM_DEVICE_BLOCK *pUmDevice) +{ + LM_DEVICE_BLOCK *pDevice = &pUmDevice->lm_dev; + LM_UINT32 buf[EEPROM_SIZE/4]; + LM_UINT8 *pdata = (LM_UINT8 *) buf; + int i; + LM_UINT32 magic, csum; + + for (i = 0; i < EEPROM_SIZE; i += 4) { + if (LM_NvramRead(pDevice, i, (LM_UINT32 *) (pdata + i)) != + LM_STATUS_SUCCESS) { + break; + } + } + if (i < EEPROM_SIZE) { + return 0; + } + + magic = MM_SWAP_BE32(buf[0]); + if (magic != 0x669955aa) { + return 0; + } + + csum = ComputeCrc32(pdata, 16); + if(csum != MM_SWAP_LE32(buf[0x10/4])) { + return 0; + } + + csum = ComputeCrc32(&pdata[0x74], 136); + if (csum != MM_SWAP_LE32(buf[0xfc/4])) { + return 0; + } + + return 1; +} + +/* Returns 1 on success, 0 on failure */ +int +b57_test_link(UM_DEVICE_BLOCK *pUmDevice) +{ + LM_DEVICE_BLOCK *pDevice = &pUmDevice->lm_dev; + LM_UINT32 phy_reg; + + if (pDevice->TbiFlags & ENABLE_TBI_FLAG) { + if (REG_RD(pDevice, MacCtrl.Status) & + (MAC_STATUS_PCS_SYNCED | MAC_STATUS_SIGNAL_DETECTED)) { + return 1; + } + return 0; + } + LM_ReadPhy(pDevice, PHY_STATUS_REG, &phy_reg); + LM_ReadPhy(pDevice, PHY_STATUS_REG, &phy_reg); + if (phy_reg & PHY_STATUS_LINK_PASS) + return 1; + return 0; +} + +/* Returns 1 on success, 0 on failure */ +int +b57_test_loopback(UM_DEVICE_BLOCK *pUmDevice) +{ + LM_DEVICE_BLOCK *pDevice = &pUmDevice->lm_dev; + struct sk_buff *skb, *rx_skb; + unsigned char *packet; + dma_addr_t map; + LM_UINT32 send_idx, rx_start_idx, rx_idx; + int num_pkts, pkt_size, i, ret; + LM_PACKET *pPacket; + T3_SND_BD *pSendBd; + T3_RCV_BD *pRcvBd; + + ret = 0; + if (!pUmDevice->opened) + return ret; + LM_ResetAdapter(pDevice); + LM_EnableMacLoopBack(pDevice); + pkt_size = 1514; + skb = dev_alloc_skb(pkt_size); + packet = skb_put(skb, pkt_size); + memcpy(packet, pDevice->NodeAddress, 6); + memset(packet + 6, 0x0, 8); + for (i = 14; i < pkt_size; i++) + packet[i] = (unsigned char) (i & 0xff); + map = pci_map_single(pUmDevice->pdev, skb->data, pkt_size, + PCI_DMA_TODEVICE); + + REG_WR(pDevice, HostCoalesce.Mode, + pDevice->CoalesceMode | HOST_COALESCE_ENABLE | + HOST_COALESCE_NOW); + MM_Wait(10); + rx_start_idx = pDevice->pStatusBlkVirt->Idx[0].RcvProdIdx; + + send_idx = 0; + num_pkts = 0; + pSendBd = &pDevice->pSendBdVirt[send_idx]; + if (pDevice->Flags & NIC_SEND_BD_FLAG) { + T3_64BIT_HOST_ADDR HostAddr; + + MM_SetT3Addr(&HostAddr, map); + MM_MEMWRITEL(&(pSendBd->HostAddr.High), HostAddr.High); + MM_MEMWRITEL(&(pSendBd->HostAddr.Low), HostAddr.Low); + MM_MEMWRITEL(&(pSendBd->u1.Len_Flags), + (pkt_size << 16) | SND_BD_FLAG_END); + send_idx++; + num_pkts++; + MB_REG_WR(pDevice, Mailbox.SendNicProdIdx[0].Low, send_idx); + if (T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5700_BX) { + MB_REG_WR(pDevice, Mailbox.SendNicProdIdx[0].Low, + send_idx); + } + MB_REG_RD(pDevice, Mailbox.SendNicProdIdx[0].Low); + } + else { + MM_SetT3Addr(&pSendBd->HostAddr, map); + pSendBd->u1.Len_Flags = (pkt_size << 16) | SND_BD_FLAG_END; + MM_WMB(); + send_idx++; + num_pkts++; + MB_REG_WR(pDevice, Mailbox.SendHostProdIdx[0].Low, send_idx); + if (T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5700_BX) { + MB_REG_WR(pDevice, Mailbox.SendHostProdIdx[0].Low, + send_idx); + } + MB_REG_RD(pDevice, Mailbox.SendHostProdIdx[0].Low); + } + MM_Wait(100); + REG_WR(pDevice, HostCoalesce.Mode, + pDevice->CoalesceMode | HOST_COALESCE_ENABLE | + HOST_COALESCE_NOW); + MM_Wait(10); + dev_kfree_skb_irq(skb); + if (pDevice->pStatusBlkVirt->Idx[0].SendConIdx != send_idx) { + goto loopback_test_done; + } + rx_idx = pDevice->pStatusBlkVirt->Idx[0].RcvProdIdx; + if (rx_idx != rx_start_idx + num_pkts) { + goto loopback_test_done; + } + pRcvBd = &pDevice->pRcvRetBdVirt[rx_start_idx]; + pPacket = (PLM_PACKET) (MM_UINT_PTR(pDevice->pPacketDescBase) + + MM_UINT_PTR(pRcvBd->Opaque)); + + if (pRcvBd->ErrorFlag && + pRcvBd->ErrorFlag != RCV_BD_ERR_ODD_NIBBLED_RCVD_MII) { + goto loopback_test_done; + } + if ((pRcvBd->Len - 4) != pkt_size) { + goto loopback_test_done; + } + rx_skb = ((UM_PACKET *) pPacket)->skbuff; + for (i = 14; i < pkt_size; i++) { + if (*(skb->data + i) != (unsigned char) (i & 0xff)) + goto loopback_test_done; + } + ret = 1; + +loopback_test_done: + LM_DisableMacLoopBack(pDevice); + return ret; +} +#endif diff -u --recursive --new-file linux-2.4.26/drivers/net/bcm/b57proc.c linux-2.4.26.patch/drivers/net/bcm/b57proc.c --- linux-2.4.26/drivers/net/bcm/b57proc.c 1969-12-31 16:00:00.000000000 -0800 +++ linux-2.4.26.patch/drivers/net/bcm/b57proc.c 2004-06-22 16:07:37.000000000 -0700 @@ -0,0 +1,473 @@ +/******************************************************************************/ +/* */ +/* Broadcom BCM5700 Linux Network Driver, Copyright (c) 2000 - 2003 Broadcom */ +/* Corporation. */ +/* All rights reserved. */ +/* */ +/* This program is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU General Public License as published by */ +/* the Free Software Foundation, located in the file LICENSE. */ +/* */ +/* /proc file system handling code. */ +/* */ +/******************************************************************************/ + +#include "mm.h" +#ifdef BCM_PROC_FS + +#define NICINFO_PROC_DIR "nicinfo" + +static struct proc_dir_entry *bcm5700_procfs_dir; + +extern char bcm5700_driver[], bcm5700_version[]; + +extern uint64_t bcm5700_crc_count(PUM_DEVICE_BLOCK pUmDevice); +extern uint64_t bcm5700_rx_err_count(PUM_DEVICE_BLOCK pUmDevice); + +static char *na_str = "n/a"; +static char *pause_str = "pause "; +static char *asym_pause_str = "asym_pause "; +static char *on_str = "on"; +static char *off_str = "off"; +static char *up_str = "up"; +static char *down_str = "down"; + +static struct proc_dir_entry * +proc_getdir(char *name, struct proc_dir_entry *proc_dir) +{ + struct proc_dir_entry *pde = proc_dir; + + lock_kernel(); + for (pde=pde->subdir; pde; pde = pde->next) { + if (pde->namelen && (strcmp(name, pde->name) == 0)) { + /* directory exists */ + break; + } + } + if (pde == (struct proc_dir_entry *) 0) + { + /* create the directory */ +#if (LINUX_VERSION_CODE > 0x20300) + pde = proc_mkdir(name, proc_dir); +#else + pde = create_proc_entry(name, S_IFDIR, proc_dir); +#endif + if (pde == (struct proc_dir_entry *) 0) { + unlock_kernel(); + return (pde); + } + } + unlock_kernel(); + return (pde); +} + +int +bcm5700_proc_create(void) +{ + bcm5700_procfs_dir = proc_getdir(NICINFO_PROC_DIR, proc_net); + + if (bcm5700_procfs_dir == (struct proc_dir_entry *) 0) { + printk(KERN_DEBUG "Could not create procfs nicinfo directory %s\n", NICINFO_PROC_DIR); + return -1; + } + return 0; +} + +void +b57_get_speed_adv(PUM_DEVICE_BLOCK pUmDevice, char *str) +{ + PLM_DEVICE_BLOCK pDevice = &pUmDevice->lm_dev; + + if (pDevice->DisableAutoNeg == TRUE) { + strcpy(str, na_str); + return; + } + if (pDevice->TbiFlags & ENABLE_TBI_FLAG) { + strcpy(str, "1000full"); + return; + } + str[0] = 0; + if (pDevice->advertising & PHY_AN_AD_10BASET_HALF) { + strcat(str, "10half "); + } + if (pDevice->advertising & PHY_AN_AD_10BASET_FULL) { + strcat(str, "10full "); + } + if (pDevice->advertising & PHY_AN_AD_100BASETX_HALF) { + strcat(str, "100half "); + } + if (pDevice->advertising & PHY_AN_AD_100BASETX_FULL) { + strcat(str, "100full "); + } + if (pDevice->advertising1000 & BCM540X_AN_AD_1000BASET_HALF) { + strcat(str, "1000half "); + } + if (pDevice->advertising1000 & BCM540X_AN_AD_1000BASET_FULL) { + strcat(str, "1000full "); + } +} + +void +b57_get_fc_adv(PUM_DEVICE_BLOCK pUmDevice, char *str) +{ + PLM_DEVICE_BLOCK pDevice = &pUmDevice->lm_dev; + + if (pDevice->DisableAutoNeg == TRUE) { + strcpy(str, na_str); + return; + } + str[0] = 0; + if (pDevice->TbiFlags & ENABLE_TBI_FLAG) { + if(pDevice->DisableAutoNeg == FALSE || + pDevice->RequestedLineSpeed == LM_LINE_SPEED_AUTO) { + if (pDevice->FlowControlCap & + LM_FLOW_CONTROL_RECEIVE_PAUSE) { + + strcpy(str, pause_str); + if (!(pDevice->FlowControlCap & + LM_FLOW_CONTROL_TRANSMIT_PAUSE)) { + + strcpy(str, asym_pause_str); + } + } + else if (pDevice->FlowControlCap & + LM_FLOW_CONTROL_TRANSMIT_PAUSE) { + + strcpy(str, asym_pause_str); + } + } + return; + } + if (pDevice->advertising & PHY_AN_AD_PAUSE_CAPABLE) { + strcat(str, pause_str); + } + if (pDevice->advertising & PHY_AN_AD_ASYM_PAUSE) { + strcat(str, asym_pause_str); + } +} + +int +bcm5700_read_pfs(char *page, char **start, off_t off, int count, + int *eof, void *data) +{ + struct net_device *dev = (struct net_device *) data; + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) dev->priv; + PLM_DEVICE_BLOCK pDevice = &pUmDevice->lm_dev; + PT3_STATS_BLOCK pStats = (PT3_STATS_BLOCK) pDevice->pStatsBlkVirt; + int len = 0; + unsigned long rx_mac_errors, rx_crc_errors, rx_align_errors; + unsigned long rx_runt_errors, rx_frag_errors, rx_long_errors; + unsigned long rx_overrun_errors, rx_jabber_errors; + char str[64]; + + if (pUmDevice->opened == 0) + pStats = 0; + + len += sprintf(page+len, "Description\t\t\t%s\n", pUmDevice->name); + len += sprintf(page+len, "Driver_Name\t\t\t%s\n", bcm5700_driver); + len += sprintf(page+len, "Driver_Version\t\t\t%s\n", bcm5700_version); + len += sprintf(page+len, "Bootcode_Version\t\t%s\n", pDevice->BootCodeVer); + len += sprintf(page+len, "PCI_Vendor\t\t\t0x%04x\n", pDevice->PciVendorId); + len += sprintf(page+len, "PCI_Device_ID\t\t\t0x%04x\n", + pDevice->PciDeviceId); + len += sprintf(page+len, "PCI_Subsystem_Vendor\t\t0x%04x\n", + pDevice->SubsystemVendorId); + len += sprintf(page+len, "PCI_Subsystem_ID\t\t0x%04x\n", + pDevice->SubsystemId); + len += sprintf(page+len, "PCI_Revision_ID\t\t\t0x%02x\n", + pDevice->PciRevId); + len += sprintf(page+len, "PCI_Slot\t\t\t%d\n", + PCI_SLOT(pUmDevice->pdev->devfn)); + if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704) { + len += sprintf(page+len, "PCI_Function\t\t\t%d\n", + pDevice->FunctNum); + } + len += sprintf(page+len, "PCI_Bus\t\t\t\t%d\n", + pUmDevice->pdev->bus->number); + + len += sprintf(page+len, "PCI_Bus_Speed\t\t\t%s\n", + pDevice->BusSpeedStr); + + len += sprintf(page+len, "Memory\t\t\t\t0x%lx\n", pUmDevice->dev->base_addr); + len += sprintf(page+len, "IRQ\t\t\t\t%d\n", dev->irq); + len += sprintf(page+len, "System_Device_Name\t\t%s\n", dev->name); + len += sprintf(page+len, "Current_HWaddr\t\t\t%02x:%02x:%02x:%02x:%02x:%02x\n", + dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2], + dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]); + len += sprintf(page+len, + "Permanent_HWaddr\t\t%02x:%02x:%02x:%02x:%02x:%02x\n", + pDevice->NodeAddress[0], pDevice->NodeAddress[1], + pDevice->NodeAddress[2], pDevice->NodeAddress[3], + pDevice->NodeAddress[4], pDevice->NodeAddress[5]); + len += sprintf(page+len, "Part_Number\t\t\t%s\n\n", pDevice->PartNo); + + len += sprintf(page+len, "Link\t\t\t\t%s\n", + (pUmDevice->opened == 0) ? "unknown" : + ((pDevice->LinkStatus == LM_STATUS_LINK_ACTIVE) ? up_str : + down_str)); + len += sprintf(page+len, "Auto_Negotiate\t\t\t%s\n", + (pDevice->DisableAutoNeg == TRUE) ? off_str : on_str); + b57_get_speed_adv(pUmDevice, str); + len += sprintf(page+len, "Speed_Advertisement\t\t%s\n", str); + b57_get_fc_adv(pUmDevice, str); + len += sprintf(page+len, "Flow_Control_Advertisement\t%s\n", str); + len += sprintf(page+len, "Speed\t\t\t\t%s\n", + ((pDevice->LinkStatus == LM_STATUS_LINK_DOWN) || + (pUmDevice->opened == 0)) ? na_str : + ((pDevice->LineSpeed == LM_LINE_SPEED_1000MBPS) ? "1000" : + ((pDevice->LineSpeed == LM_LINE_SPEED_100MBPS) ? "100" : + (pDevice->LineSpeed == LM_LINE_SPEED_10MBPS) ? "10" : na_str))); + len += sprintf(page+len, "Duplex\t\t\t\t%s\n", + ((pDevice->LinkStatus == LM_STATUS_LINK_DOWN) || + (pUmDevice->opened == 0)) ? na_str : + ((pDevice->DuplexMode == LM_DUPLEX_MODE_FULL) ? "full" : + "half")); + len += sprintf(page+len, "Flow_Control\t\t\t%s\n", + ((pDevice->LinkStatus == LM_STATUS_LINK_DOWN) || + (pUmDevice->opened == 0)) ? na_str : + ((pDevice->FlowControl == LM_FLOW_CONTROL_NONE) ? off_str : + (((pDevice->FlowControl & LM_FLOW_CONTROL_RX_TX_PAUSE) == + LM_FLOW_CONTROL_RX_TX_PAUSE) ? "receive/transmit" : + (pDevice->FlowControl & LM_FLOW_CONTROL_RECEIVE_PAUSE) ? + "receive" : "transmit"))); + len += sprintf(page+len, "State\t\t\t\t%s\n", + (pUmDevice->suspended ? "suspended" : + ((dev->flags & IFF_UP) ? up_str : down_str))); + len += sprintf(page+len, "MTU_Size\t\t\t%d\n\n", dev->mtu); + len += sprintf(page+len, "Rx_Packets\t\t\t%lu\n", + ((pStats == 0) ? 0 : + MM_GETSTATS(pStats->ifHCInUcastPkts) + + MM_GETSTATS(pStats->ifHCInMulticastPkts) + + MM_GETSTATS(pStats->ifHCInBroadcastPkts))); +#if T3_JUMBO_RCV_RCB_ENTRY_COUNT + if (dev->mtu > 1500) { + len += sprintf(page+len, "Rx_Jumbo_Packets\t\t%lu\n", + ((pStats == 0) ? 0 : + MM_GETSTATS( + pStats->etherStatsPkts1523Octetsto2047Octets) + + MM_GETSTATS( + pStats->etherStatsPkts2048Octetsto4095Octets) + + MM_GETSTATS( + pStats->etherStatsPkts4096Octetsto8191Octets) + + MM_GETSTATS( + pStats->etherStatsPkts8192Octetsto9022Octets))); + } +#endif + len += sprintf(page+len, "Tx_Packets\t\t\t%lu\n", + ((pStats == 0) ? 0 : + MM_GETSTATS(pStats->ifHCOutUcastPkts) + + MM_GETSTATS(pStats->ifHCOutMulticastPkts) + + MM_GETSTATS(pStats->ifHCOutBroadcastPkts))); +#ifdef BCM_TSO + len += sprintf(page+len, "TSO_Large_Packets\t\t%lu\n", + pUmDevice->tso_pkt_count); +#endif + len += sprintf(page+len, "Rx_Bytes\t\t\t%lu\n", + ((pStats == 0) ? 0 : + MM_GETSTATS(pStats->ifHCInOctets))); + len += sprintf(page+len, "Tx_Bytes\t\t\t%lu\n", + ((pStats == 0) ? 0 : + MM_GETSTATS(pStats->ifHCOutOctets))); + if (pStats == 0) { + rx_crc_errors = 0; + rx_align_errors = 0; + rx_runt_errors = 0; + rx_frag_errors = 0; + rx_long_errors = 0; + rx_overrun_errors = 0; + rx_jabber_errors = 0; + } + else { + rx_crc_errors = (unsigned long) bcm5700_crc_count(pUmDevice); + rx_align_errors = MM_GETSTATS(pStats->dot3StatsAlignmentErrors); + rx_runt_errors = MM_GETSTATS(pStats->etherStatsUndersizePkts); + rx_frag_errors = MM_GETSTATS(pStats->etherStatsFragments); + rx_long_errors = MM_GETSTATS(pStats->dot3StatsFramesTooLong); + rx_overrun_errors = MM_GETSTATS(pStats->nicNoMoreRxBDs); + rx_jabber_errors = MM_GETSTATS(pStats->etherStatsJabbers); + } + rx_mac_errors = (unsigned long) bcm5700_rx_err_count(pUmDevice); + len += sprintf(page+len, "Rx_Errors\t\t\t%lu\n", + ((pStats == 0) ? 0 : + rx_mac_errors + rx_overrun_errors + pUmDevice->rx_misc_errors)); + len += sprintf(page+len, "Tx_Errors\t\t\t%lu\n", + ((pStats == 0) ? 0 : + MM_GETSTATS(pStats->ifOutErrors))); + len += sprintf(page+len, "\nTx_Carrier_Errors\t\t%lu\n", + ((pStats == 0) ? 0 : + MM_GETSTATS(pStats->dot3StatsCarrierSenseErrors))); + len += sprintf(page+len, "Tx_Abort_Excess_Coll\t\t%lu\n", + ((pStats == 0) ? 0 : + MM_GETSTATS(pStats->dot3StatsExcessiveCollisions))); + len += sprintf(page+len, "Tx_Abort_Late_Coll\t\t%lu\n", + ((pStats == 0) ? 0 : + MM_GETSTATS(pStats->dot3StatsLateCollisions))); + len += sprintf(page+len, "Tx_Deferred_Ok\t\t\t%lu\n", + ((pStats == 0) ? 0 : + MM_GETSTATS(pStats->dot3StatsDeferredTransmissions))); + len += sprintf(page+len, "Tx_Single_Coll_Ok\t\t%lu\n", + ((pStats == 0) ? 0 : + MM_GETSTATS(pStats->dot3StatsSingleCollisionFrames))); + len += sprintf(page+len, "Tx_Multi_Coll_Ok\t\t%lu\n", + ((pStats == 0) ? 0 : + MM_GETSTATS(pStats->dot3StatsMultipleCollisionFrames))); + len += sprintf(page+len, "Tx_Total_Coll_Ok\t\t%lu\n", + ((pStats == 0) ? 0 : + MM_GETSTATS(pStats->etherStatsCollisions))); + len += sprintf(page+len, "Tx_XON_Pause_Frames\t\t%lu\n", + ((pStats == 0) ? 0 : + MM_GETSTATS(pStats->outXonSent))); + len += sprintf(page+len, "Tx_XOFF_Pause_Frames\t\t%lu\n", + ((pStats == 0) ? 0 : + MM_GETSTATS(pStats->outXoffSent))); + len += sprintf(page+len, "\nRx_CRC_Errors\t\t\t%lu\n", rx_crc_errors); + len += sprintf(page+len, "Rx_Short_Fragment_Errors\t%lu\n", + rx_frag_errors); + len += sprintf(page+len, "Rx_Short_Length_Errors\t\t%lu\n", + rx_runt_errors); + len += sprintf(page+len, "Rx_Long_Length_Errors\t\t%lu\n", + rx_long_errors); + len += sprintf(page+len, "Rx_Align_Errors\t\t\t%lu\n", + rx_align_errors); + len += sprintf(page+len, "Rx_Overrun_Errors\t\t%lu\n", + rx_overrun_errors); + len += sprintf(page+len, "Rx_XON_Pause_Frames\t\t%lu\n", + ((pStats == 0) ? 0 : + MM_GETSTATS(pStats->xonPauseFramesReceived))); + len += sprintf(page+len, "Rx_XOFF_Pause_Frames\t\t%lu\n", + ((pStats == 0) ? 0 : + MM_GETSTATS(pStats->xoffPauseFramesReceived))); + len += sprintf(page+len, "\nTx_MAC_Errors\t\t\t%lu\n", + ((pStats == 0) ? 0 : + MM_GETSTATS(pStats->dot3StatsInternalMacTransmitErrors))); + len += sprintf(page+len, "Rx_MAC_Errors\t\t\t%lu\n\n", + rx_mac_errors); + + len += sprintf(page+len, "Tx_Checksum\t\t\t%s\n", + ((pDevice->TaskToOffload & LM_TASK_OFFLOAD_TX_TCP_CHECKSUM) ? + on_str : off_str)); + len += sprintf(page+len, "Rx_Checksum\t\t\t%s\n", + ((pDevice->TaskToOffload & LM_TASK_OFFLOAD_RX_TCP_CHECKSUM) ? + on_str : off_str)); + len += sprintf(page+len, "Scatter_Gather\t\t\t%s\n", +#if (LINUX_VERSION_CODE >= 0x20400) + ((dev->features & NETIF_F_SG) ? on_str : off_str)); +#else + off_str); +#endif +#ifdef BCM_TSO + len += sprintf(page+len, "TSO\t\t\t\t%s\n", + ((dev->features & NETIF_F_TSO) ? on_str : off_str)); +#endif + len += sprintf(page+len, "VLAN\t\t\t\t%s\n\n", + ((pDevice->RxMode & RX_MODE_KEEP_VLAN_TAG) ? off_str : on_str)); + +#ifdef BCM_NIC_SEND_BD + len += sprintf(page+len, "NIC_Tx_BDs\t\t\t%s\n", + (pDevice->Flags & NIC_SEND_BD_FLAG) ? on_str : off_str); +#endif + len += sprintf(page+len, "Tx_Desc_Count\t\t\t%u\n", + pDevice->TxPacketDescCnt); + len += sprintf(page+len, "Rx_Desc_Count\t\t\t%u\n", + pDevice->RxStdDescCnt); +#if T3_JUMBO_RCV_RCB_ENTRY_COUNT + len += sprintf(page+len, "Rx_Jumbo_Desc_Count\t\t%u\n", + pDevice->RxJumboDescCnt); +#endif +#ifdef BCM_INT_COAL + len += sprintf(page+len, "Adaptive_Coalescing\t\t%s\n", + (pUmDevice->adaptive_coalesce ? on_str : off_str)); + len += sprintf(page+len, "Rx_Coalescing_Ticks\t\t%u\n", + pUmDevice->rx_curr_coalesce_ticks); + len += sprintf(page+len, "Rx_Coalesced_Frames\t\t%u\n", + pUmDevice->rx_curr_coalesce_frames); + len += sprintf(page+len, "Tx_Coalescing_Ticks\t\t%u\n", + pDevice->TxCoalescingTicks); + len += sprintf(page+len, "Tx_Coalesced_Frames\t\t%u\n", + pUmDevice->tx_curr_coalesce_frames); + len += sprintf(page+len, "Stats_Coalescing_Ticks\t\t%u\n", + pDevice->StatsCoalescingTicks); +#endif +#ifdef BCM_WOL + len += sprintf(page+len, "Wake_On_LAN\t\t\t%s\n", + ((pDevice->WakeUpMode & LM_WAKE_UP_MODE_MAGIC_PACKET) ? + on_str : off_str)); +#endif +#if TIGON3_DEBUG + len += sprintf(page+len, "\nDmaReadWriteCtrl\t\t%x\n", + pDevice->DmaReadWriteCtrl); + len += sprintf(page+len, "\nTx_Zero_Copy_Packets\t\t%u\n", + pUmDevice->tx_zc_count); + len += sprintf(page+len, "Tx_Chksum_Packets\t\t%u\n", + pUmDevice->tx_chksum_count); + len += sprintf(page+len, "Tx_Highmem_Fragments\t\t%u\n", + pUmDevice->tx_himem_count); + len += sprintf(page+len, "Rx_Good_Chksum_Packets\t\t%u\n", + pUmDevice->rx_good_chksum_count); + len += sprintf(page+len, "Rx_Bad_Chksum_Packets\t\t%u\n", + pUmDevice->rx_bad_chksum_count); + if (!(pDevice->TbiFlags & ENABLE_TBI_FLAG)) { + LM_UINT32 value32; + unsigned long flags; + + BCM5700_PHY_LOCK(pUmDevice, flags); + LM_ReadPhy(pDevice, 0, &value32); + len += sprintf(page+len, "\nPhy_Register_0x00\t\t0x%x\n", value32); + LM_ReadPhy(pDevice, 1, &value32); + len += sprintf(page+len, "Phy_Register_0x01\t\t0x%x\n", value32); + LM_ReadPhy(pDevice, 2, &value32); + len += sprintf(page+len, "Phy_Register_0x02\t\t0x%x\n", value32); + LM_ReadPhy(pDevice, 3, &value32); + len += sprintf(page+len, "Phy_Register_0x03\t\t0x%x\n", value32); + LM_ReadPhy(pDevice, 4, &value32); + len += sprintf(page+len, "Phy_Register_0x04\t\t0x%x\n", value32); + LM_ReadPhy(pDevice, 5, &value32); + len += sprintf(page+len, "Phy_Register_0x05\t\t0x%x\n", value32); + LM_ReadPhy(pDevice, 9, &value32); + len += sprintf(page+len, "Phy_Register_0x09\t\t0x%x\n", value32); + LM_ReadPhy(pDevice, 0xa, &value32); + len += sprintf(page+len, "Phy_Register_0x0A\t\t0x%x\n", value32); + LM_ReadPhy(pDevice, 0xf, &value32); + len += sprintf(page+len, "Phy_Register_0x0F\t\t0x%x\n", value32); + LM_ReadPhy(pDevice, 0x10, &value32); + len += sprintf(page+len, "Phy_Register_0x10\t\t0x%x\n", value32); + LM_ReadPhy(pDevice, 0x19, &value32); + len += sprintf(page+len, "Phy_Register_0x19\t\t0x%x\n", value32); + LM_WritePhy(pDevice, 0x18, 0x0007); + LM_ReadPhy(pDevice, 0x18, &value32); + len += sprintf(page+len, "Phy_Register_0x18_00\t\t0x%x\n", value32); + BCM5700_PHY_UNLOCK(pUmDevice, flags); + } +#endif + + *eof = 1; + return len; +} + +int +bcm5700_proc_create_dev(struct net_device *dev) +{ + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) dev->priv; + + if (!bcm5700_procfs_dir) + return -1; + + sprintf(pUmDevice->pfs_name, "%s.info", dev->name); + pUmDevice->pfs_entry = create_proc_entry(pUmDevice->pfs_name, + S_IFREG, bcm5700_procfs_dir); + if (pUmDevice->pfs_entry == 0) + return -1; + pUmDevice->pfs_entry->read_proc = bcm5700_read_pfs; + pUmDevice->pfs_entry->data = dev; + return 0; +} +int +bcm5700_proc_remove_dev(struct net_device *dev) +{ + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) dev->priv; + + remove_proc_entry(pUmDevice->pfs_name, bcm5700_procfs_dir); + return 0; +} + +#endif diff -u --recursive --new-file linux-2.4.26/drivers/net/bcm/b57um.c linux-2.4.26.patch/drivers/net/bcm/b57um.c --- linux-2.4.26/drivers/net/bcm/b57um.c 1969-12-31 16:00:00.000000000 -0800 +++ linux-2.4.26.patch/drivers/net/bcm/b57um.c 2004-06-22 16:21:25.000000000 -0700 @@ -0,0 +1,4981 @@ +/******************************************************************************/ +/* */ +/* Broadcom BCM5700 Linux Network Driver, Copyright (c) 2000 - 2004 Broadcom */ +/* Corporation. */ +/* All rights reserved. */ +/* */ +/* This program is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU General Public License as published by */ +/* the Free Software Foundation, located in the file LICENSE. */ +/* */ +/******************************************************************************/ + + +char bcm5700_driver[] = "bcm5700"; +char bcm5700_version[] = "7.3.5"; +char bcm5700_date[] = "(06/23/04)"; + +#define B57UM +#include "mm.h" + +/* A few user-configurable values. */ + +#define MAX_UNITS 16 +/* Used to pass the full-duplex flag, etc. */ +static int line_speed[MAX_UNITS] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}; +static int auto_speed[MAX_UNITS] = {1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1}; +static int full_duplex[MAX_UNITS] = {1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1}; +static int rx_flow_control[MAX_UNITS] = {1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1}; +static int tx_flow_control[MAX_UNITS] = {1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1}; +static int auto_flow_control[MAX_UNITS] = {1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1}; +#if T3_JUMBO_RCV_RCB_ENTRY_COUNT +static int mtu[MAX_UNITS] = {1500,1500,1500,1500,1500,1500,1500,1500,1500,1500,1500,1500,1500,1500,1500,1500}; /* Jumbo MTU for interfaces. */ +#endif +static int tx_checksum[MAX_UNITS] = {1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1}; +static int rx_checksum[MAX_UNITS] = {1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1}; +static int scatter_gather[MAX_UNITS] = {1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1}; + +#define TX_DESC_CNT DEFAULT_TX_PACKET_DESC_COUNT +static unsigned int tx_pkt_desc_cnt[MAX_UNITS] = + {TX_DESC_CNT,TX_DESC_CNT,TX_DESC_CNT,TX_DESC_CNT,TX_DESC_CNT, + TX_DESC_CNT,TX_DESC_CNT,TX_DESC_CNT,TX_DESC_CNT,TX_DESC_CNT, + TX_DESC_CNT,TX_DESC_CNT,TX_DESC_CNT,TX_DESC_CNT,TX_DESC_CNT, + TX_DESC_CNT}; + +#define RX_DESC_CNT DEFAULT_STD_RCV_DESC_COUNT +static unsigned int rx_std_desc_cnt[MAX_UNITS] = + {RX_DESC_CNT,RX_DESC_CNT,RX_DESC_CNT,RX_DESC_CNT,RX_DESC_CNT, + RX_DESC_CNT,RX_DESC_CNT,RX_DESC_CNT,RX_DESC_CNT,RX_DESC_CNT, + RX_DESC_CNT,RX_DESC_CNT,RX_DESC_CNT,RX_DESC_CNT,RX_DESC_CNT, + RX_DESC_CNT }; + +#if T3_JUMBO_RCV_RCB_ENTRY_COUNT +#define JBO_DESC_CNT DEFAULT_JUMBO_RCV_DESC_COUNT +static unsigned int rx_jumbo_desc_cnt[MAX_UNITS] = + {JBO_DESC_CNT,JBO_DESC_CNT,JBO_DESC_CNT,JBO_DESC_CNT,JBO_DESC_CNT, + JBO_DESC_CNT,JBO_DESC_CNT,JBO_DESC_CNT,JBO_DESC_CNT,JBO_DESC_CNT, + JBO_DESC_CNT,JBO_DESC_CNT,JBO_DESC_CNT,JBO_DESC_CNT,JBO_DESC_CNT, + JBO_DESC_CNT }; +#endif + +#ifdef BCM_INT_COAL +#ifdef BCM_NAPI_RXPOLL +static unsigned int adaptive_coalesce[MAX_UNITS] = + {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}; +#else +static unsigned int adaptive_coalesce[MAX_UNITS] = + {1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1}; +#endif + +#define RX_COAL_TK DEFAULT_RX_COALESCING_TICKS +static unsigned int rx_coalesce_ticks[MAX_UNITS] = + {RX_COAL_TK,RX_COAL_TK,RX_COAL_TK,RX_COAL_TK,RX_COAL_TK, + RX_COAL_TK, RX_COAL_TK,RX_COAL_TK,RX_COAL_TK,RX_COAL_TK, + RX_COAL_TK,RX_COAL_TK, RX_COAL_TK,RX_COAL_TK,RX_COAL_TK, + RX_COAL_TK}; + +#define RX_COAL_FM DEFAULT_RX_MAX_COALESCED_FRAMES +static unsigned int rx_max_coalesce_frames[MAX_UNITS] = + {RX_COAL_FM,RX_COAL_FM,RX_COAL_FM,RX_COAL_FM,RX_COAL_FM, + RX_COAL_FM,RX_COAL_FM,RX_COAL_FM,RX_COAL_FM,RX_COAL_FM, + RX_COAL_FM,RX_COAL_FM,RX_COAL_FM,RX_COAL_FM,RX_COAL_FM, + RX_COAL_FM}; + +#define TX_COAL_TK DEFAULT_TX_COALESCING_TICKS +static unsigned int tx_coalesce_ticks[MAX_UNITS] = + {TX_COAL_TK,TX_COAL_TK,TX_COAL_TK,TX_COAL_TK,TX_COAL_TK, + TX_COAL_TK, TX_COAL_TK,TX_COAL_TK,TX_COAL_TK,TX_COAL_TK, + TX_COAL_TK,TX_COAL_TK, TX_COAL_TK,TX_COAL_TK,TX_COAL_TK, + TX_COAL_TK}; + +#define TX_COAL_FM DEFAULT_TX_MAX_COALESCED_FRAMES +static unsigned int tx_max_coalesce_frames[MAX_UNITS] = + {TX_COAL_FM,TX_COAL_FM,TX_COAL_FM,TX_COAL_FM,TX_COAL_FM, + TX_COAL_FM,TX_COAL_FM,TX_COAL_FM,TX_COAL_FM,TX_COAL_FM, + TX_COAL_FM,TX_COAL_FM,TX_COAL_FM,TX_COAL_FM,TX_COAL_FM, + TX_COAL_FM}; + +#define ST_COAL_TK DEFAULT_STATS_COALESCING_TICKS +static unsigned int stats_coalesce_ticks[MAX_UNITS] = + {ST_COAL_TK,ST_COAL_TK,ST_COAL_TK,ST_COAL_TK,ST_COAL_TK, + ST_COAL_TK,ST_COAL_TK,ST_COAL_TK,ST_COAL_TK,ST_COAL_TK, + ST_COAL_TK,ST_COAL_TK,ST_COAL_TK,ST_COAL_TK,ST_COAL_TK, + ST_COAL_TK,}; + +#endif +#ifdef BCM_WOL +static int enable_wol[MAX_UNITS] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}; +#endif +#ifdef BCM_TSO +static int enable_tso[MAX_UNITS] = {1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1}; +#endif +#ifdef BCM_NIC_SEND_BD +static int nic_tx_bd[MAX_UNITS] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}; +#endif +#ifdef BCM_ASF +static int vlan_tag_mode[MAX_UNITS] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}; +#endif +#ifdef INCLUDE_5750_A0_FIX +static int shasta_smp_fix[MAX_UNITS] = {1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1}; +#endif +static int delay_link[MAX_UNITS] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}; +static int disable_d3hot[MAX_UNITS] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}; + +/* Operational parameters that usually are not changed. */ +/* Time in jiffies before concluding the transmitter is hung. */ +#define TX_TIMEOUT (2*HZ) + +#if (LINUX_VERSION_CODE < 0x02030d) +#define pci_resource_start(dev, bar) (dev->base_address[bar] & PCI_BASE_ADDRESS_MEM_MASK) +#elif (LINUX_VERSION_CODE < 0x02032b) +#define pci_resource_start(dev, bar) (dev->resource[bar] & PCI_BASE_ADDRESS_MEM_MASK) +#endif + +#if (LINUX_VERSION_CODE < 0x02032b) +#define dev_kfree_skb_irq(skb) dev_kfree_skb(skb) +#define netif_wake_queue(dev) clear_bit(0, &dev->tbusy); mark_bh(NET_BH) +#define netif_stop_queue(dev) set_bit(0, &dev->tbusy) + +static inline void netif_start_queue(struct net_device *dev) +{ + dev->tbusy = 0; + dev->interrupt = 0; + dev->start = 1; +} + +#define netif_queue_stopped(dev) dev->tbusy +#define netif_running(dev) dev->start + +static inline void tasklet_schedule(struct tasklet_struct *tasklet) +{ + queue_task(tasklet, &tq_immediate); + mark_bh(IMMEDIATE_BH); +} + +static inline void tasklet_init(struct tasklet_struct *tasklet, + void (*func)(unsigned long), + unsigned long data) +{ + tasklet->next = NULL; + tasklet->sync = 0; + tasklet->routine = (void (*)(void *))func; + tasklet->data = (void *)data; +} + +#define tasklet_kill(tasklet) + +#endif + +#if (LINUX_VERSION_CODE < 0x020300) +struct pci_device_id { + unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */ + unsigned int subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */ + unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */ + unsigned long driver_data; /* Data private to the driver */ +}; + +#define PCI_ANY_ID 0 + +#define pci_set_drvdata(pdev, dev) +#define pci_get_drvdata(pdev) 0 + +#define pci_enable_device(pdev) 0 + +#define __devinit __init +#define __devinitdata __initdata +#define __devexit + +#define SET_MODULE_OWNER(dev) +#define MODULE_DEVICE_TABLE(pci, pci_tbl) + +#endif + +#if (LINUX_VERSION_CODE < 0x020411) +#ifndef __devexit_p +#define __devexit_p(x) x +#endif +#endif + +#ifndef MODULE_LICENSE +#define MODULE_LICENSE(license) +#endif + +#ifndef IRQ_RETVAL +typedef void irqreturn_t; +#define IRQ_RETVAL(x) +#endif + +#if (LINUX_VERSION_CODE < 0x02032a) +static inline void *pci_alloc_consistent(struct pci_dev *pdev, size_t size, + dma_addr_t *dma_handle) +{ + void *virt_ptr; + + /* Maximum in slab.c */ + if (size > 131072) + return 0; + + virt_ptr = kmalloc(size, GFP_KERNEL); + *dma_handle = virt_to_bus(virt_ptr); + return virt_ptr; +} +#define pci_free_consistent(dev, size, ptr, dma_ptr) kfree(ptr) + +#endif /*#if (LINUX_VERSION_CODE < 0x02032a) */ + + +#if (LINUX_VERSION_CODE < 0x02040d) + +#if (LINUX_VERSION_CODE >= 0x020409) && defined(RED_HAT_LINUX_KERNEL) + +#define BCM_32BIT_DMA_MASK ((u64) 0x00000000ffffffffULL) +#define BCM_64BIT_DMA_MASK ((u64) 0xffffffffffffffffULL) + +#else +/* pci_set_dma_mask is using dma_addr_t */ + +#define BCM_32BIT_DMA_MASK ((dma_addr_t) 0xffffffff) +#define BCM_64BIT_DMA_MASK ((dma_addr_t) 0xffffffff) + +#endif + +#else /* (LINUX_VERSION_CODE < 0x02040d) */ + +#define BCM_32BIT_DMA_MASK ((u64) 0x00000000ffffffffULL) +#define BCM_64BIT_DMA_MASK ((u64) 0xffffffffffffffffULL) +#endif + +#if (LINUX_VERSION_CODE < 0x020329) +#define pci_set_dma_mask(pdev, mask) (0) +#else +#if (LINUX_VERSION_CODE < 0x020403) +int +pci_set_dma_mask(struct pci_dev *dev, dma_addr_t mask) +{ + if(! pci_dma_supported(dev, mask)) + return -EIO; + + dev->dma_mask = mask; + + return 0; +} +#endif +#endif + +#if (LINUX_VERSION_CODE < 0x020547) +#define pci_set_consistent_dma_mask(pdev, mask) (0) +#endif + +#if (LINUX_VERSION_CODE < 0x020402) +#define pci_request_regions(pdev, name) (0) +#define pci_release_regions(pdev) +#endif + +#if ! defined(spin_is_locked) +#define spin_is_locked(lock) (test_bit(0,(lock))) +#endif + +#define BCM5700_LOCK(pUmDevice, flags) \ + if ((pUmDevice)->do_global_lock) { \ + spin_lock_irqsave(&(pUmDevice)->global_lock, flags); \ + } + +#define BCM5700_UNLOCK(pUmDevice, flags) \ + if ((pUmDevice)->do_global_lock) { \ + spin_unlock_irqrestore(&(pUmDevice)->global_lock, flags);\ + } + +inline void +bcm5700_intr_lock(PUM_DEVICE_BLOCK pUmDevice) +{ + if (pUmDevice->do_global_lock) { + spin_lock(&pUmDevice->global_lock); + } +} + +inline void +bcm5700_intr_unlock(PUM_DEVICE_BLOCK pUmDevice) +{ + if (pUmDevice->do_global_lock) { + spin_unlock(&pUmDevice->global_lock); + } +} + +void +bcm5700_intr_off(PUM_DEVICE_BLOCK pUmDevice) +{ + atomic_inc(&pUmDevice->intr_sem); + LM_DisableInterrupt(&pUmDevice->lm_dev); +#if (LINUX_VERSION_CODE >= 0x2051c) + synchronize_irq(pUmDevice->dev->irq); +#else + synchronize_irq(); +#endif + LM_DisableInterrupt(&pUmDevice->lm_dev); +} + +void +bcm5700_intr_on(PUM_DEVICE_BLOCK pUmDevice) +{ + if (atomic_dec_and_test(&pUmDevice->intr_sem)) { + LM_EnableInterrupt(&pUmDevice->lm_dev); + } +} + +/* + * Broadcom NIC Extension support + * -ffan + */ +#ifdef NICE_SUPPORT +#include "nicext.h" + +typedef struct { + ushort tag; + ushort signature; +} vlan_tag_t; + +#endif /* NICE_SUPPORT */ + +int MM_Packet_Desc_Size = sizeof(UM_PACKET); + +#if defined(MODULE) +MODULE_AUTHOR("Michael Chan "); +MODULE_DESCRIPTION("BCM5700 Driver"); +MODULE_LICENSE("GPL"); +MODULE_PARM(debug, "i"); +MODULE_PARM(line_speed, "1-" __MODULE_STRING(MAX_UNITS) "i"); +MODULE_PARM(auto_speed, "1-" __MODULE_STRING(MAX_UNITS) "i"); +MODULE_PARM(full_duplex, "1-" __MODULE_STRING(MAX_UNITS) "i"); +MODULE_PARM(rx_flow_control, "1-" __MODULE_STRING(MAX_UNITS) "i"); +MODULE_PARM(tx_flow_control, "1-" __MODULE_STRING(MAX_UNITS) "i"); +MODULE_PARM(auto_flow_control, "1-" __MODULE_STRING(MAX_UNITS) "i"); +#if T3_JUMBO_RCV_RCB_ENTRY_COUNT +MODULE_PARM(mtu, "1-" __MODULE_STRING(MAX_UNITS) "i"); +#endif +MODULE_PARM(tx_checksum, "1-" __MODULE_STRING(MAX_UNITS) "i"); +MODULE_PARM(rx_checksum, "1-" __MODULE_STRING(MAX_UNITS) "i"); +MODULE_PARM(scatter_gather, "1-" __MODULE_STRING(MAX_UNITS) "i"); +MODULE_PARM(tx_pkt_desc_cnt, "1-" __MODULE_STRING(MAX_UNITS) "i"); +MODULE_PARM(rx_std_desc_cnt, "1-" __MODULE_STRING(MAX_UNITS) "i"); +#if T3_JUMBO_RCV_RCB_ENTRY_COUNT +MODULE_PARM(rx_jumbo_desc_cnt, "1-" __MODULE_STRING(MAX_UNITS) "i"); +#endif +#ifdef BCM_INT_COAL +MODULE_PARM(adaptive_coalesce, "1-" __MODULE_STRING(MAX_UNITS) "i"); +MODULE_PARM(rx_coalesce_ticks, "1-" __MODULE_STRING(MAX_UNITS) "i"); +MODULE_PARM(rx_max_coalesce_frames, "1-" __MODULE_STRING(MAX_UNITS) "i"); +MODULE_PARM(tx_coalesce_ticks, "1-" __MODULE_STRING(MAX_UNITS) "i"); +MODULE_PARM(tx_max_coalesce_frames, "1-" __MODULE_STRING(MAX_UNITS) "i"); +MODULE_PARM(stats_coalesce_ticks, "1-" __MODULE_STRING(MAX_UNITS) "i"); +#endif +#ifdef BCM_WOL +MODULE_PARM(enable_wol, "1-" __MODULE_STRING(MAX_UNITS) "i"); +#endif +#ifdef BCM_TSO +MODULE_PARM(enable_tso, "1-" __MODULE_STRING(MAX_UNITS) "i"); +#endif +#ifdef BCM_NIC_SEND_BD +MODULE_PARM(nic_tx_bd, "1-" __MODULE_STRING(MAX_UNITS) "i"); +#endif +#ifdef BCM_ASF +MODULE_PARM(vlan_tag_mode, "1-" __MODULE_STRING(MAX_UNITS) "i"); +#endif +#ifdef INCLUDE_5750_A0_FIX +MODULE_PARM(shasta_smp_fix, "1-" __MODULE_STRING(MAX_UNITS) "i"); +#endif +MODULE_PARM(delay_link, "1-" __MODULE_STRING(MAX_UNITS) "i"); +MODULE_PARM(disable_d3hot, "1-" __MODULE_STRING(MAX_UNITS) "i"); +#endif + +#define RUN_AT(x) (jiffies + (x)) + +char kernel_version[] = UTS_RELEASE; + +#define PCI_SUPPORT_VER2 + +#if ! defined(CAP_NET_ADMIN) +#define capable(CAP_XXX) (suser()) +#endif + +#define tigon3_debug debug +#if TIGON3_DEBUG +static int tigon3_debug = TIGON3_DEBUG; +#else +static int tigon3_debug = 0; +#endif + + +STATIC int bcm5700_open(struct net_device *dev); +STATIC void bcm5700_timer(unsigned long data); +STATIC void bcm5700_reset(struct net_device *dev); +STATIC int bcm5700_start_xmit(struct sk_buff *skb, struct net_device *dev); +STATIC irqreturn_t bcm5700_interrupt(int irq, void *dev_instance, struct pt_regs *regs); +#ifdef BCM_TASKLET +STATIC void bcm5700_tasklet(unsigned long data); +#endif +STATIC int bcm5700_close(struct net_device *dev); +STATIC struct net_device_stats *bcm5700_get_stats(struct net_device *dev); +STATIC int bcm5700_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); +STATIC void bcm5700_set_rx_mode(struct net_device *dev); +STATIC int bcm5700_set_mac_addr(struct net_device *dev, void *p); +#if T3_JUMBO_RCV_RCB_ENTRY_COUNT +STATIC int bcm5700_change_mtu(struct net_device *dev, int new_mtu); +#endif +#ifdef BCM_NAPI_RXPOLL +STATIC int bcm5700_poll(struct net_device *dev, int *budget); +#endif +STATIC int replenish_rx_buffers(PUM_DEVICE_BLOCK pUmDevice, int max); +STATIC int bcm5700_freemem(struct net_device *dev); +#ifdef NICE_SUPPORT +STATIC int bcm5700_freemem2(UM_DEVICE_BLOCK *pUmDevice, int index); +#endif +#ifdef BCM_INT_COAL +#ifndef BCM_NAPI_RXPOLL +STATIC int bcm5700_adapt_coalesce(PUM_DEVICE_BLOCK pUmDevice); +#endif +#endif +STATIC void bcm5700_set_vlan_mode(UM_DEVICE_BLOCK *pUmDevice); +STATIC int bcm5700_init_counters(PUM_DEVICE_BLOCK pUmDevice); +#ifdef BCM_VLAN +STATIC void bcm5700_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp); +STATIC void bcm5700_vlan_rx_kill_vid(struct net_device *dev, uint16_t vid); +#endif +void bcm5700_shutdown(UM_DEVICE_BLOCK *pUmDevice); +void bcm5700_free_remaining_rx_bufs(UM_DEVICE_BLOCK *pUmDevice); +void bcm5700_validate_param_range(UM_DEVICE_BLOCK *pUmDevice, int *param, + char *param_name, int min, int max, int deflt); + +#ifdef HAVE_POLL_CONTROLLER +STATIC void poll_bcm5700(struct net_device *dev); +#endif + +/* A list of all installed bcm5700 devices. */ +static struct net_device *root_tigon3_dev = NULL; + +#if defined(CONFIG_SPARC64) || defined(CONFIG_X86_64) ||defined(CONFIG_PPC64) + +#ifdef NICE_SUPPORT +#if (LINUX_VERSION_CODE < 0x20500) +extern int register_ioctl32_conversion(unsigned int cmd, + int (*handler)(unsigned int, unsigned int, unsigned long, + struct file *)); +int unregister_ioctl32_conversion(unsigned int cmd); +#else +#include +#endif + +#define BCM_IOCTL32 1 + +atomic_t bcm5700_load_count = ATOMIC_INIT(0); + +static int +bcm5700_ioctl32(unsigned int fd, unsigned int cmd, unsigned long arg, + struct file *filep) +{ + struct ifreq rq; + struct net_device *tmp_dev = root_tigon3_dev; + int ret; + struct nice_req* nrq; + struct ifreq_nice32 { + char ifnr_name[16]; + __u32 cmd; + __u32 nrq1; + __u32 nrq2; + __u32 nrq3; + } nrq32; + + if (!capable(CAP_NET_ADMIN)) + return -EPERM; + + if (copy_from_user(&nrq32, (char *) arg, 32)) + return -EFAULT; + + memcpy(rq.ifr_name, nrq32.ifnr_name, 16); + + nrq = (struct nice_req*) &rq.ifr_ifru; + nrq->cmd = nrq32.cmd; + if (nrq->cmd == NICE_CMD_GET_STATS_BLOCK) { + nrq->nrq_stats_useraddr = (void *) ((__u64) nrq32.nrq1); + nrq->nrq_stats_size = nrq32.nrq2; + } + else { + memcpy(&nrq->nrq_speed, &nrq32.nrq1, 12); + } + while (tmp_dev) { + if (strcmp(rq.ifr_name, tmp_dev->name) == 0) { + ret = bcm5700_ioctl(tmp_dev, &rq, cmd); + if (ret == 0) { + if (nrq->cmd == NICE_CMD_GET_STATS_BLOCK) + return ret; + + memcpy(&nrq32.nrq1, &nrq->nrq_speed, 12); + if (copy_to_user((char *) arg, &nrq32, 32)) + return -EFAULT; + } + return ret; + } + tmp_dev = ((UM_DEVICE_BLOCK *)(tmp_dev->priv))->next_module; + } + return -ENODEV; +} +#endif /* NICE_SUPPORT */ +#endif + +typedef enum { + BCM5700A6 = 0, + BCM5700T6, + BCM5700A9, + BCM5700T9, + BCM5700, + BCM5701A5, + BCM5701T1, + BCM5701T8, + BCM5701A7, + BCM5701A10, + BCM5701A12, + BCM5701, + BCM5702, + BCM5703, + BCM5703A31, + BCM5703ARBUCKLE, + TC996T, + TC996ST, + TC996SSX, + TC996SX, + TC996BT, + TC997T, + TC997SX, + TC1000T, + TC1000BT, + TC940BR01, + TC942BR01, + TC998T, + TC998SX, + TC999T, + NC6770, + NC1020, + NC150T, + NC7760, + NC7761, + NC7770, + NC7771, + NC7780, + NC7781, + NC7772, + NC7782, + NC7783, + NC320T, + BCM5704CIOBE, + BCM5704, + BCM5704S, + BCM5705, + BCM5705M, + BCM5705F, + BCM5901, + BCM5782, + BCM5788, + BCM5789, + BCM5750, + BCM5750M, + BCM5720, + BCM5751, + BCM5751M, + BCM5751F, + BCM5721, +} board_t; + + +/* indexed by board_t, above */ +static struct { + char *name; +} board_info[] __devinitdata = { + { "Broadcom BCM5700 1000Base-T" }, + { "Broadcom BCM5700 1000Base-SX" }, + { "Broadcom BCM5700 1000Base-SX" }, + { "Broadcom BCM5700 1000Base-T" }, + { "Broadcom BCM5700" }, + { "Broadcom BCM5701 1000Base-T" }, + { "Broadcom BCM5701 1000Base-T" }, + { "Broadcom BCM5701 1000Base-T" }, + { "Broadcom BCM5701 1000Base-SX" }, + { "Broadcom BCM5701 1000Base-T" }, + { "Broadcom BCM5701 1000Base-T" }, + { "Broadcom BCM5701" }, + { "Broadcom BCM5702 1000Base-T" }, + { "Broadcom BCM5703 1000Base-T" }, + { "Broadcom BCM5703 1000Base-SX" }, + { "Broadcom B5703 1000Base-SX" }, + { "3Com 3C996 10/100/1000 Server NIC" }, + { "3Com 3C996 10/100/1000 Server NIC" }, + { "3Com 3C996 Gigabit Fiber-SX Server NIC" }, + { "3Com 3C996 Gigabit Fiber-SX Server NIC" }, + { "3Com 3C996B Gigabit Server NIC" }, + { "3Com 3C997 Gigabit Server NIC" }, + { "3Com 3C997 Gigabit Fiber-SX Server NIC" }, + { "3Com 3C1000 Gigabit NIC" }, + { "3Com 3C1000B-T 10/100/1000 PCI" }, + { "3Com 3C940 Gigabit LOM (21X21)" }, + { "3Com 3C942 Gigabit LOM (31X31)" }, + { "3Com 3C998-T Dual Port 10/100/1000 PCI-X Server NIC" }, + { "3Com 3C998-SX Dual Port 1000-SX PCI-X Server NIC" }, + { "3Com 3C999-T Quad Port 10/100/1000 PCI-X Server NIC" }, + { "HP NC6770 Gigabit Server Adapter" }, + { "NC1020 HP ProLiant Gigabit Server Adapter 32 PCI" }, + { "HP ProLiant NC 150T PCI 4-port Gigabit Combo Switch Adapter" }, + { "HP NC7760 Gigabit Server Adapter" }, + { "HP NC7761 Gigabit Server Adapter" }, + { "HP NC7770 Gigabit Server Adapter" }, + { "HP NC7771 Gigabit Server Adapter" }, + { "HP NC7780 Gigabit Server Adapter" }, + { "HP NC7781 Gigabit Server Adapter" }, + { "HP NC7772 Gigabit Server Adapter" }, + { "HP NC7782 Gigabit Server Adapter" }, + { "HP NC7783 Gigabit Server Adapter" }, + { "HP ProLiant NC 320T PCI Express Gigabit Server Adapter" }, + { "Broadcom BCM5704 CIOB-E 1000Base-T" }, + { "Broadcom BCM5704 1000Base-T" }, + { "Broadcom BCM5704 1000Base-SX" }, + { "Broadcom BCM5705 1000Base-T" }, + { "Broadcom BCM5705M 1000Base-T" }, + { "Broadcom 570x 10/100 Integrated Controller" }, + { "Broadcom BCM5901 100Base-TX" }, + { "Broadcom NetXtreme Gigabit Ethernet for hp" }, + { "Broadcom BCM5788 NetLink 1000Base-T" }, + { "Broadcom BCM5789 NetLink 1000Base-T PCI Express" }, + { "Broadcom BCM5750 1000Base-T PCI" }, + { "Broadcom BCM5750M 1000Base-T PCI" }, + { "Broadcom BCM5720 1000Base-T PCI" }, + { "Broadcom BCM5751 1000Base-T PCI Express" }, + { "Broadcom BCM5751M 1000Base-T PCI Express" }, + { "Broadcom BCM5751F 100Base-TX PCI Express" }, + { "Broadcom BCM5721 1000Base-T PCI Express" }, + { 0 }, + }; + +static struct pci_device_id bcm5700_pci_tbl[] __devinitdata = { + {0x14e4, 0x1644, 0x14e4, 0x1644, 0, 0, BCM5700A6 }, + {0x14e4, 0x1644, 0x14e4, 0x2, 0, 0, BCM5700T6 }, + {0x14e4, 0x1644, 0x14e4, 0x3, 0, 0, BCM5700A9 }, + {0x14e4, 0x1644, 0x14e4, 0x4, 0, 0, BCM5700T9 }, + {0x14e4, 0x1644, 0x1028, 0xd1, 0, 0, BCM5700 }, + {0x14e4, 0x1644, 0x1028, 0x0106, 0, 0, BCM5700 }, + {0x14e4, 0x1644, 0x1028, 0x0109, 0, 0, BCM5700 }, + {0x14e4, 0x1644, 0x1028, 0x010a, 0, 0, BCM5700 }, + {0x14e4, 0x1644, 0x10b7, 0x1000, 0, 0, TC996T }, + {0x14e4, 0x1644, 0x10b7, 0x1001, 0, 0, TC996ST }, + {0x14e4, 0x1644, 0x10b7, 0x1002, 0, 0, TC996SSX }, + {0x14e4, 0x1644, 0x10b7, 0x1003, 0, 0, TC997T }, + {0x14e4, 0x1644, 0x10b7, 0x1005, 0, 0, TC997SX }, + {0x14e4, 0x1644, 0x10b7, 0x1008, 0, 0, TC942BR01 }, + {0x14e4, 0x1644, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5700 }, + {0x14e4, 0x1645, 0x14e4, 1, 0, 0, BCM5701A5 }, + {0x14e4, 0x1645, 0x14e4, 5, 0, 0, BCM5701T1 }, + {0x14e4, 0x1645, 0x14e4, 6, 0, 0, BCM5701T8 }, + {0x14e4, 0x1645, 0x14e4, 7, 0, 0, BCM5701A7 }, + {0x14e4, 0x1645, 0x14e4, 8, 0, 0, BCM5701A10 }, + {0x14e4, 0x1645, 0x14e4, 0x8008, 0, 0, BCM5701A12 }, + {0x14e4, 0x1645, 0x0e11, 0xc1, 0, 0, NC6770 }, + {0x14e4, 0x1645, 0x0e11, 0x7c, 0, 0, NC7770 }, + {0x14e4, 0x1645, 0x0e11, 0x85, 0, 0, NC7780 }, + {0x14e4, 0x1645, 0x1028, 0x0121, 0, 0, BCM5701 }, + {0x14e4, 0x1645, 0x10b7, 0x1004, 0, 0, TC996SX }, + {0x14e4, 0x1645, 0x10b7, 0x1006, 0, 0, TC996BT }, + {0x14e4, 0x1645, 0x10b7, 0x1007, 0, 0, TC1000T }, + {0x14e4, 0x1645, 0x10b7, 0x1008, 0, 0, TC940BR01 }, + {0x14e4, 0x1645, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5701 }, + {0x14e4, 0x1646, 0x14e4, 0x8009, 0, 0, BCM5702 }, + {0x14e4, 0x1646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5702 }, + {0x14e4, 0x16a6, 0x14e4, 0x8009, 0, 0, BCM5702 }, + {0x14e4, 0x16a6, 0x14e4, 0x000c, 0, 0, BCM5702 }, + {0x14e4, 0x16a6, 0x0e11, 0xbb, 0, 0, NC7760 }, + {0x14e4, 0x16a6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5702 }, + {0x14e4, 0x16c6, 0x10b7, 0x1100, 0, 0, TC1000BT }, + {0x14e4, 0x16c6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5702 }, + {0x14e4, 0x1647, 0x14e4, 0x0009, 0, 0, BCM5703 }, + {0x14e4, 0x1647, 0x14e4, 0x000a, 0, 0, BCM5703A31 }, + {0x14e4, 0x1647, 0x14e4, 0x000b, 0, 0, BCM5703 }, + {0x14e4, 0x1647, 0x14e4, 0x800a, 0, 0, BCM5703 }, + {0x14e4, 0x1647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5703 }, + {0x14e4, 0x16a7, 0x14e4, 0x0009, 0, 0, BCM5703 }, + {0x14e4, 0x16a7, 0x14e4, 0x000a, 0, 0, BCM5703A31 }, + {0x14e4, 0x16a7, 0x14e4, 0x000b, 0, 0, BCM5703 }, + {0x14e4, 0x16a7, 0x14e4, 0x800a, 0, 0, BCM5703 }, + {0x14e4, 0x16a7, 0x0e11, 0xca, 0, 0, NC7771 }, + {0x14e4, 0x16a7, 0x0e11, 0xcb, 0, 0, NC7781 }, + {0x14e4, 0x16a7, 0x1014, 0x0281, 0, 0, BCM5703ARBUCKLE }, + {0x14e4, 0x16a7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5703 }, + {0x14e4, 0x16c7, 0x14e4, 0x000a, 0, 0, BCM5703A31 }, + {0x14e4, 0x16c7, 0x0e11, 0xca, 0, 0, NC7771 }, + {0x14e4, 0x16c7, 0x0e11, 0xcb, 0, 0, NC7781 }, + {0x14e4, 0x16c7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5703 }, + {0x14e4, 0x1648, 0x0e11, 0xcf, 0, 0, NC7772 }, + {0x14e4, 0x1648, 0x0e11, 0xd0, 0, 0, NC7782 }, + {0x14e4, 0x1648, 0x0e11, 0xd1, 0, 0, NC7783 }, + {0x14e4, 0x1648, 0x10b7, 0x2000, 0, 0, TC998T }, + {0x14e4, 0x1648, 0x10b7, 0x3000, 0, 0, TC999T }, + {0x14e4, 0x1648, 0x1166, 0x1648, 0, 0, BCM5704CIOBE }, + {0x14e4, 0x1648, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5704 }, + {0x14e4, 0x1649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5704S }, + {0x14e4, 0x16a8, 0x14e4, 0x16a8, 0, 0, BCM5704S }, + {0x14e4, 0x16a8, 0x10b7, 0x2001, 0, 0, TC998SX }, + {0x14e4, 0x16a8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5704S }, + {0x14e4, 0x1653, 0x0e11, 0x00e3, 0, 0, NC7761 }, + {0x14e4, 0x1653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5705 }, + {0x14e4, 0x1654, 0x0e11, 0x00e3, 0, 0, NC7761 }, + {0x14e4, 0x1654, 0x103c, 0x3100, 0, 0, NC1020 }, + {0x14e4, 0x1654, 0x103c, 0x3226, 0, 0, NC150T }, + {0x14e4, 0x1654, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5705 }, + {0x14e4, 0x165d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5705M }, + {0x14e4, 0x165e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5705M }, + {0x14e4, 0x166e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5705F }, + {0x14e4, 0x1696, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5782 }, + {0x14e4, 0x169c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5788 }, + {0x14e4, 0x169d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5789 }, + {0x14e4, 0x170d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5901 }, + {0x14e4, 0x170e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5901 }, + {0x14e4, 0x1676, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5750 }, + {0x14e4, 0x167c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5750M }, + {0x14e4, 0x1677, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5751 }, + {0x14e4, 0x167d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5751M }, + {0x14e4, 0x167e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5751F }, + {0x14e4, 0x1658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5720 }, + {0x14e4, 0x1659, 0x103c, 0x7031, 0, 0, NC320T }, + {0x14e4, 0x1659, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5721 }, + {0,} +}; + +MODULE_DEVICE_TABLE(pci, bcm5700_pci_tbl); + +#ifdef BCM_PROC_FS +extern int bcm5700_proc_create(void); +extern int bcm5700_proc_create_dev(struct net_device *dev); +extern int bcm5700_proc_remove_dev(struct net_device *dev); +#endif + +static int __devinit bcm5700_init_board(struct pci_dev *pdev, + struct net_device **dev_out, + int board_idx) +{ + struct net_device *dev; + PUM_DEVICE_BLOCK pUmDevice; + PLM_DEVICE_BLOCK pDevice; + int rc; + + *dev_out = NULL; + + /* dev zeroed in init_etherdev */ +#if (LINUX_VERSION_CODE >= 0x20600) + dev = alloc_etherdev(sizeof(*pUmDevice)); +#else + dev = init_etherdev(NULL, sizeof(*pUmDevice)); +#endif + if (dev == NULL) { + printk (KERN_ERR "%s: unable to alloc new ethernet\n", + bcm5700_driver); + return -ENOMEM; + } + SET_MODULE_OWNER(dev); +#if (LINUX_VERSION_CODE >= 0x20600) + SET_NETDEV_DEV(dev, &pdev->dev); +#endif + pUmDevice = (PUM_DEVICE_BLOCK) dev->priv; + + /* enable device (incl. PCI PM wakeup), and bus-mastering */ + rc = pci_enable_device (pdev); + if (rc) + goto err_out; + + rc = pci_request_regions(pdev, bcm5700_driver); + if (rc) + goto err_out; + + pci_set_master(pdev); + + if (pci_set_dma_mask(pdev, BCM_64BIT_DMA_MASK) == 0) { + pUmDevice->using_dac = 1; + if (pci_set_consistent_dma_mask(pdev, BCM_64BIT_DMA_MASK) != 0) + { + printk(KERN_ERR "pci_set_consistent_dma_mask failed\n"); + pci_release_regions(pdev); + goto err_out; + } + } + else if (pci_set_dma_mask(pdev, BCM_32BIT_DMA_MASK) == 0) { + pUmDevice->using_dac = 0; + } + else { + printk(KERN_ERR "System does not support DMA\n"); + pci_release_regions(pdev); + goto err_out; + } + + pUmDevice->dev = dev; + pUmDevice->pdev = pdev; + pUmDevice->mem_list_num = 0; + pUmDevice->next_module = root_tigon3_dev; + pUmDevice->index = board_idx; + root_tigon3_dev = dev; + + spin_lock_init(&pUmDevice->global_lock); + + spin_lock_init(&pUmDevice->undi_lock); + + spin_lock_init(&pUmDevice->phy_lock); + + pDevice = (PLM_DEVICE_BLOCK) pUmDevice; + pDevice->Flags = 0; + pDevice->FunctNum = PCI_FUNC(pUmDevice->pdev->devfn); + +#if T3_JUMBO_RCV_RCB_ENTRY_COUNT + bcm5700_validate_param_range(pUmDevice, &mtu[board_idx], "mtu", 1500, 9000, 1500); + dev->mtu = mtu[board_idx]; +#endif + + if (pci_find_device(0x8086, 0x2418, NULL) || + pci_find_device(0x8086, 0x2428, NULL) || + pci_find_device(0x8086, 0x244e, NULL) || + pci_find_device(0x8086, 0x2448, NULL)) { + + /* Found ICH, ICH0, or ICH2 */ + pDevice->Flags |= UNDI_FIX_FLAG; + } + + if (LM_GetAdapterInfo(pDevice) != LM_STATUS_SUCCESS) { + printk(KERN_ERR "Get Adapter info failed\n"); + rc = -ENODEV; + goto err_out_unmap; + } + + if (T3_ASIC_5705_OR_5750(pDevice->ChipRevId)) { + if (dev->mtu > 1500) { + dev->mtu = 1500; + printk(KERN_WARNING "%s-%d: Jumbo mtu sizes not supported, using mtu=1500\n", bcm5700_driver, pUmDevice->index); + } + } + + if (pci_find_device(0x1022, 0x700c, NULL)) { + /* AMD762 writes I/O out of order */ + /* Setting bit 1 in 762's register 0x4C still doesn't work */ + /* in all cases */ + pDevice->Flags |= FLUSH_POSTED_WRITE_FLAG; + pDevice->Flags &= ~NIC_SEND_BD_FLAG; + } + pUmDevice->do_global_lock = 0; + if (T3_ASIC_REV(pUmDevice->lm_dev.ChipRevId) == T3_ASIC_REV_5700) { + /* The 5700 chip works best without interleaved register */ + /* accesses on certain machines. */ + pUmDevice->do_global_lock = 1; + } +#ifdef INCLUDE_5750_A0_FIX + if ((pDevice->Flags & PCI_EXPRESS_FLAG) && + (pDevice->ChipRevId == T3_CHIP_ID_5750_A0)) + { + if (shasta_smp_fix[pUmDevice->index]) { + pUmDevice->do_global_lock = 1; + pDevice->Flags |= (FLUSH_POSTED_WRITE_FLAG | + REG_RD_BACK_FLAG); + } + else { + pDevice->Flags &= ~REG_RD_BACK_FLAG; + } + } +#endif + if ((T3_ASIC_REV(pUmDevice->lm_dev.ChipRevId) == T3_ASIC_REV_5701) && + ((pDevice->PciState & T3_PCI_STATE_NOT_PCI_X_BUS) == 0)) { + + pUmDevice->rx_buf_align = 0; + } + else { + pUmDevice->rx_buf_align = 2; + } +/* dev->base_addr = pci_resource_start(pdev, 0);*/ + dev->mem_start = pci_resource_start(pdev, 0); + dev->mem_end = dev->mem_start + sizeof(T3_STD_MEM_MAP); + dev->irq = pdev->irq; + + *dev_out = dev; + return 0; + +err_out_unmap: + pci_release_regions(pdev); + bcm5700_freemem(dev); + +err_out: +#if (LINUX_VERSION_CODE < 0x020600) + unregister_netdev(dev); + kfree(dev); +#else + free_netdev(dev); +#endif + return rc; +} + +static int __devinit +bcm5700_print_ver(void) +{ + printk(KERN_INFO "Broadcom Gigabit Ethernet Driver %s ", + bcm5700_driver); +#ifdef NICE_SUPPORT + printk("with Broadcom NIC Extension (NICE) "); +#endif + printk("ver. %s %s\n", bcm5700_version, bcm5700_date); + return 0; +} + +static int __devinit +bcm5700_init_one(struct pci_dev *pdev, + const struct pci_device_id *ent) +{ + struct net_device *dev = NULL; + PUM_DEVICE_BLOCK pUmDevice; + PLM_DEVICE_BLOCK pDevice; + int i; + static int board_idx = -1; + static int printed_version = 0; + struct pci_dev *amd_dev; + + board_idx++; + + if (!printed_version) { + bcm5700_print_ver(); +#ifdef BCM_PROC_FS + bcm5700_proc_create(); +#endif + printed_version = 1; + } + + i = bcm5700_init_board(pdev, &dev, board_idx); + if (i < 0) { + return i; + } + + if (dev == NULL) + return -ENOMEM; + +#ifdef BCM_IOCTL32 + if (atomic_read(&bcm5700_load_count) == 0) { + register_ioctl32_conversion(SIOCNICE, bcm5700_ioctl32); + } + atomic_inc(&bcm5700_load_count); +#endif + dev->open = bcm5700_open; + dev->hard_start_xmit = bcm5700_start_xmit; + dev->stop = bcm5700_close; + dev->get_stats = bcm5700_get_stats; + dev->set_multicast_list = bcm5700_set_rx_mode; + dev->do_ioctl = bcm5700_ioctl; + dev->set_mac_address = &bcm5700_set_mac_addr; +#if T3_JUMBO_RCV_RCB_ENTRY_COUNT + dev->change_mtu = &bcm5700_change_mtu; +#endif +#if (LINUX_VERSION_CODE >= 0x20400) + dev->tx_timeout = bcm5700_reset; + dev->watchdog_timeo = TX_TIMEOUT; +#endif +#ifdef BCM_VLAN + dev->vlan_rx_register = &bcm5700_vlan_rx_register; + dev->vlan_rx_kill_vid = &bcm5700_vlan_rx_kill_vid; +#endif +#ifdef BCM_NAPI_RXPOLL + dev->poll = bcm5700_poll; + dev->weight = 64; +#endif + + pUmDevice = (PUM_DEVICE_BLOCK) dev->priv; + pDevice = (PLM_DEVICE_BLOCK) pUmDevice; + + dev->base_addr = pci_resource_start(pdev, 0); + dev->irq = pdev->irq; +#ifdef HAVE_POLL_CONTROLLER + dev->poll_controller = poll_bcm5700; +#endif + +#if (LINUX_VERSION_CODE >= 0x20600) + if ((i = register_netdev(dev))) { + printk(KERN_ERR "%s: Cannot register net device\n", + bcm5700_driver); + if (pUmDevice->lm_dev.pMappedMemBase) + iounmap(pUmDevice->lm_dev.pMappedMemBase); + pci_release_regions(pdev); + bcm5700_freemem(dev); + free_netdev(dev); + return i; + } +#endif + + pci_set_drvdata(pdev, dev); + + memcpy(dev->dev_addr, pDevice->NodeAddress, 6); + pUmDevice->name = board_info[ent->driver_data].name, + printk(KERN_INFO "%s: %s found at mem %lx, IRQ %d, ", + dev->name, pUmDevice->name, dev->base_addr, + dev->irq); + printk("node addr "); + for (i = 0; i < 6; i++) { + printk("%2.2x", dev->dev_addr[i]); + } + printk("\n"); + + printk(KERN_INFO "%s: ", dev->name); + if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5400_PHY_ID) + printk("Broadcom BCM5400 Copper "); + else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5401_PHY_ID) + printk("Broadcom BCM5401 Copper "); + else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5411_PHY_ID) + printk("Broadcom BCM5411 Copper "); + else if (((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5701_PHY_ID) && + !(pDevice->TbiFlags & ENABLE_TBI_FLAG)) { + printk("Broadcom BCM5701 Integrated Copper "); + } + else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5703_PHY_ID) { + printk("Broadcom BCM5703 Integrated "); + if (pDevice->TbiFlags & ENABLE_TBI_FLAG) + printk("SerDes "); + else + printk("Copper "); + } + else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5704_PHY_ID) { + printk("Broadcom BCM5704 Integrated "); + if (pDevice->TbiFlags & ENABLE_TBI_FLAG) + printk("SerDes "); + else + printk("Copper "); + } + else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5705_PHY_ID) + printk("Broadcom BCM5705 Integrated Copper "); + else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5750_PHY_ID) + printk("Broadcom BCM5750 Integrated Copper "); + else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM8002_PHY_ID) + printk("Broadcom BCM8002 SerDes "); + else if (pDevice->TbiFlags & ENABLE_TBI_FLAG) { + if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703) { + printk("Broadcom BCM5703 Integrated SerDes "); + } + else if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704) { + printk("Broadcom BCM5704 Integrated SerDes "); + } + else { + printk("Agilent HDMP-1636 SerDes "); + } + } + else { + printk("Unknown "); + } + printk("transceiver found\n"); + + printk(KERN_INFO "%s: ", dev->name); +#if (LINUX_VERSION_CODE >= 0x20400) + if (scatter_gather[board_idx]) { + dev->features |= NETIF_F_SG; + if (pUmDevice->using_dac && !(pDevice->Flags & BCM5788_FLAG)) + dev->features |= NETIF_F_HIGHDMA; + } + if ((pDevice->TaskOffloadCap & LM_TASK_OFFLOAD_TX_TCP_CHECKSUM) && + tx_checksum[board_idx]) { + dev->features |= NETIF_F_IP_CSUM; + } +#ifdef BCM_VLAN + dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; +#endif +#ifdef BCM_TSO + if ((pDevice->TaskToOffload & LM_TASK_OFFLOAD_TCP_SEGMENTATION) && + enable_tso[board_idx]) { + dev->features |= NETIF_F_TSO; + } +#endif + + printk("Scatter-gather %s, 64-bit DMA %s, Tx Checksum %s, ", + (char *) ((dev->features & NETIF_F_SG) ? "ON" : "OFF"), + (char *) ((dev->features & NETIF_F_HIGHDMA) ? "ON" : "OFF"), + (char *) ((dev->features & NETIF_F_IP_CSUM) ? "ON" : "OFF")); +#endif + if ((pDevice->ChipRevId != T3_CHIP_ID_5700_B0) && + rx_checksum[board_idx]) + printk("Rx Checksum ON"); + else + printk("Rx Checksum OFF"); +#ifdef BCM_VLAN + printk(", 802.1Q VLAN ON"); +#endif +#ifdef BCM_TSO + if (dev->features & NETIF_F_TSO) { + printk(", TSO ON"); + } + else +#endif +#ifdef BCM_NAPI_RXPOLL + printk(", NAPI ON"); +#endif + printk("\n"); + +#ifdef BCM_PROC_FS + bcm5700_proc_create_dev(dev); +#endif +#ifdef BCM_TASKLET + tasklet_init(&pUmDevice->tasklet, bcm5700_tasklet, + (unsigned long) pUmDevice); +#endif + if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704) { + if ((REG_RD(pDevice, PciCfg.DualMacCtrl) & + T3_DUAL_MAC_CH_CTRL_MASK) == 3) { + + printk(KERN_WARNING "%s: Device is configured for Hardware Based Teaming which is not supported with this operating system. Please consult the user diagnostic guide to disable Turbo Teaming.\n", dev->name); + } + } + + if ((amd_dev = pci_find_device(0x1022, 0x700c, NULL))) { + u32 val; + + /* Found AMD 762 North bridge */ + pci_read_config_dword(amd_dev, 0x4c, &val); + if ((val & 0x02) == 0) { + pci_write_config_dword(amd_dev, 0x4c, val | 0x02); + printk(KERN_INFO "%s: Setting AMD762 Northbridge to enable PCI ordering compliance\n", bcm5700_driver); + } + } + return 0; + +} + + +static void __devexit +bcm5700_remove_one (struct pci_dev *pdev) +{ + struct net_device *dev = pci_get_drvdata (pdev); + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK)dev->priv; + +#ifdef BCM_PROC_FS + bcm5700_proc_remove_dev(dev); +#endif +#ifdef BCM_IOCTL32 + atomic_dec(&bcm5700_load_count); + if (atomic_read(&bcm5700_load_count) == 0) + unregister_ioctl32_conversion(SIOCNICE); +#endif + unregister_netdev(dev); + + if (pUmDevice->lm_dev.pMappedMemBase) + iounmap(pUmDevice->lm_dev.pMappedMemBase); + + pci_release_regions(pdev); + +#if (LINUX_VERSION_CODE < 0x020600) + kfree(dev); +#else + free_netdev(dev); +#endif + + pci_set_drvdata(pdev, NULL); + +/* pci_power_off(pdev, -1);*/ + +} + + + +STATIC int +bcm5700_open(struct net_device *dev) +{ + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK)dev->priv; + PLM_DEVICE_BLOCK pDevice = (PLM_DEVICE_BLOCK) pUmDevice; + + if (pUmDevice->suspended) + return -EAGAIN; + + /* delay for 6 seconds */ + pUmDevice->delayed_link_ind = (6 * HZ) / pUmDevice->timer_interval; + +#ifdef BCM_INT_COAL +#ifndef BCM_NAPI_RXPOLL + pUmDevice->adaptive_expiry = HZ / pUmDevice->timer_interval; +#endif +#endif + +#if INCLUDE_TBI_SUPPORT + if ((pDevice->TbiFlags & ENABLE_TBI_FLAG) && + (pDevice->TbiFlags & TBI_POLLING_FLAGS)) { + pUmDevice->poll_tbi_interval = HZ / pUmDevice->timer_interval; + if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703) { + pUmDevice->poll_tbi_interval /= 4; + } + pUmDevice->poll_tbi_expiry = pUmDevice->poll_tbi_interval; + } +#endif + + pUmDevice->asf_heartbeat = (120 * HZ) / pUmDevice->timer_interval; + + pUmDevice->stats_interval = HZ / pUmDevice->timer_interval; + + /* Sometimes we get spurious ints. after reset when link is down. */ + /* This field tells the isr to service the int. even if there is */ + /* no status block update. */ + if (pDevice->LedCtrl != LED_CTRL_PHY_MODE_2) { + pUmDevice->adapter_just_inited = (3 * HZ) / + pUmDevice->timer_interval; + } + else { + pUmDevice->adapter_just_inited = 0; + } + + if (request_irq(dev->irq, &bcm5700_interrupt, SA_SHIRQ, dev->name, dev)) { + return -EAGAIN; + } + + pUmDevice->opened = 1; + if (LM_InitializeAdapter(pDevice) != LM_STATUS_SUCCESS) { + pUmDevice->opened = 0; + free_irq(dev->irq, dev); + bcm5700_freemem(dev); + return -EAGAIN; + } + + bcm5700_set_vlan_mode(pUmDevice); + bcm5700_init_counters(pUmDevice); + + if (pDevice->Flags & UNDI_FIX_FLAG) { + printk(KERN_INFO "%s: Using indirect register access\n", dev->name); + } + + if (memcmp(dev->dev_addr, pDevice->NodeAddress, 6)) { + LM_SetMacAddress(pDevice, dev->dev_addr); + } + + if (tigon3_debug > 1) + printk(KERN_DEBUG "%s: tigon3_open() irq %d.\n", dev->name, dev->irq); + + QQ_InitQueue(&pUmDevice->rx_out_of_buf_q.Container, + MAX_RX_PACKET_DESC_COUNT); + netif_start_queue(dev); + +#if (LINUX_VERSION_CODE < 0x020300) + MOD_INC_USE_COUNT; +#endif + + init_timer(&pUmDevice->timer); + pUmDevice->timer.expires = RUN_AT(pUmDevice->timer_interval); + pUmDevice->timer.data = (unsigned long)dev; + pUmDevice->timer.function = &bcm5700_timer; + add_timer(&pUmDevice->timer); + + atomic_set(&pUmDevice->intr_sem, 0); + LM_EnableInterrupt(pDevice); + + return 0; +} + + +STATIC void +bcm5700_timer(unsigned long data) +{ + struct net_device *dev = (struct net_device *)data; + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK)dev->priv; + PLM_DEVICE_BLOCK pDevice = (PLM_DEVICE_BLOCK) pUmDevice; + unsigned long flags = 0; + LM_UINT32 value32; + + if (!pUmDevice->opened) + return; + + if (atomic_read(&pUmDevice->intr_sem) || pUmDevice->suspended) { + pUmDevice->timer.expires = RUN_AT(pUmDevice->timer_interval); + add_timer(&pUmDevice->timer); + return; + } + + if (T3_ASIC_5705_OR_5750(pDevice->ChipRevId) && + (pDevice->LinkStatus == LM_STATUS_LINK_ACTIVE) && + (--pUmDevice->stats_interval <= 0)) { + + BCM5700_LOCK(pUmDevice, flags); + LM_GetStats(pDevice); + BCM5700_UNLOCK(pUmDevice, flags); + pUmDevice->stats_interval = HZ / pUmDevice->timer_interval; + } + +#if INCLUDE_TBI_SUPPORT + if ((pDevice->TbiFlags & TBI_POLLING_FLAGS) && + (--pUmDevice->poll_tbi_expiry <= 0)) { + + BCM5700_PHY_LOCK(pUmDevice, flags); + value32 = REG_RD(pDevice, MacCtrl.Status); + if (((pDevice->LinkStatus == LM_STATUS_LINK_ACTIVE) && + ((value32 & (MAC_STATUS_LINK_STATE_CHANGED | + MAC_STATUS_CFG_CHANGED)) || + !(value32 & MAC_STATUS_PCS_SYNCED))) + || + ((pDevice->LinkStatus != LM_STATUS_LINK_ACTIVE) && + (value32 & (MAC_STATUS_PCS_SYNCED | + MAC_STATUS_SIGNAL_DETECTED)))) + { + LM_SetupPhy(pDevice); + } + BCM5700_PHY_UNLOCK(pUmDevice, flags); + pUmDevice->poll_tbi_expiry = pUmDevice->poll_tbi_interval; + + } +#endif + + if (pUmDevice->delayed_link_ind > 0) { + if (pUmDevice->delayed_link_ind == 1) + MM_IndicateStatus(pDevice, pDevice->LinkStatus); + else + pUmDevice->delayed_link_ind--; + } + if (pUmDevice->adapter_just_inited > 0) { + pUmDevice->adapter_just_inited--; + } + + if (pUmDevice->crc_counter_expiry > 0) + pUmDevice->crc_counter_expiry--; + + if (!pUmDevice->interrupt) { + if (!(pDevice->Flags & USE_TAGGED_STATUS_FLAG)) { + BCM5700_LOCK(pUmDevice, flags); + if (pDevice->pStatusBlkVirt->Status & STATUS_BLOCK_UPDATED) { + /* This will generate an interrupt */ + REG_WR(pDevice, Grc.LocalCtrl, + pDevice->GrcLocalCtrl | + GRC_MISC_LOCAL_CTRL_SET_INT); + } + else { + REG_WR(pDevice, HostCoalesce.Mode, + pDevice->CoalesceMode | + HOST_COALESCE_ENABLE | + HOST_COALESCE_NOW); + } + if (!(REG_RD(pDevice, DmaWrite.Mode) & + DMA_WRITE_MODE_ENABLE)) { + BCM5700_UNLOCK(pUmDevice, flags); + bcm5700_reset(dev); + } + else { + BCM5700_UNLOCK(pUmDevice, flags); + } + if (pUmDevice->tx_queued) { + pUmDevice->tx_queued = 0; + netif_wake_queue(dev); + } + } +#if (LINUX_VERSION_CODE < 0x02032b) + if ((QQ_GetEntryCnt(&pDevice->TxPacketFreeQ.Container) != + pDevice->TxPacketDescCnt) && + ((jiffies - dev->trans_start) > TX_TIMEOUT)) { + + printk(KERN_WARNING "%s: Tx hung\n", dev->name); + bcm5700_reset(dev); + } +#endif + } +#ifdef BCM_INT_COAL +#ifndef BCM_NAPI_RXPOLL + if (pUmDevice->adaptive_coalesce) { + pUmDevice->adaptive_expiry--; + if (pUmDevice->adaptive_expiry == 0) { + pUmDevice->adaptive_expiry = HZ / + pUmDevice->timer_interval; + bcm5700_adapt_coalesce(pUmDevice); + } + } +#endif +#endif + if (QQ_GetEntryCnt(&pUmDevice->rx_out_of_buf_q.Container) > + (unsigned int) pUmDevice->rx_buf_repl_panic_thresh) { + /* Generate interrupt and let isr allocate buffers */ + REG_WR(pDevice, HostCoalesce.Mode, pDevice->CoalesceMode | + HOST_COALESCE_ENABLE | HOST_COALESCE_NOW); + } + +#ifdef BCM_ASF + if (pDevice->AsfFlags & ASF_ENABLED) { + pUmDevice->asf_heartbeat--; + if (pUmDevice->asf_heartbeat == 0) { + MEM_WR_OFFSET(pDevice, T3_CMD_MAILBOX, + T3_CMD_NICDRV_ALIVE); + MEM_WR_OFFSET(pDevice, T3_CMD_LENGTH_MAILBOX, 4); + MEM_WR_OFFSET(pDevice, T3_CMD_DATA_MAILBOX, 3); + value32 = REG_RD(pDevice, Grc.RxCpuEvent); + REG_WR(pDevice, Grc.RxCpuEvent, value32 | BIT_14); + pUmDevice->asf_heartbeat = (120 * HZ) / + pUmDevice->timer_interval; + } + } +#endif + + pUmDevice->timer.expires = RUN_AT(pUmDevice->timer_interval); + add_timer(&pUmDevice->timer); +} + +STATIC int +bcm5700_init_counters(PUM_DEVICE_BLOCK pUmDevice) +{ +#ifdef BCM_INT_COAL +#ifndef BCM_NAPI_RXPOLL + LM_DEVICE_BLOCK *pDevice = &pUmDevice->lm_dev; + + pUmDevice->rx_curr_coalesce_frames = pDevice->RxMaxCoalescedFrames; + pUmDevice->rx_curr_coalesce_ticks = pDevice->RxCoalescingTicks; + pUmDevice->tx_curr_coalesce_frames = pDevice->TxMaxCoalescedFrames; + pUmDevice->rx_last_cnt = 0; + pUmDevice->tx_last_cnt = 0; +#endif +#endif + pUmDevice->phy_crc_count = 0; +#if TIGON3_DEBUG + pUmDevice->tx_zc_count = 0; + pUmDevice->tx_chksum_count = 0; + pUmDevice->tx_himem_count = 0; + pUmDevice->rx_good_chksum_count = 0; + pUmDevice->rx_bad_chksum_count = 0; +#endif +#ifdef BCM_TSO + pUmDevice->tso_pkt_count = 0; +#endif + return 0; +} + +#ifdef BCM_INT_COAL +#ifndef BCM_NAPI_RXPOLL +STATIC int +bcm5700_do_adapt_coalesce(PUM_DEVICE_BLOCK pUmDevice, + int rx_frames, int rx_ticks, int tx_frames, int rx_frames_intr) +{ + unsigned long flags = 0; + LM_DEVICE_BLOCK *pDevice = &pUmDevice->lm_dev; + + if (pUmDevice->do_global_lock) { + if (spin_is_locked(&pUmDevice->global_lock)) + return 0; + spin_lock_irqsave(&pUmDevice->global_lock, flags); + } + pUmDevice->rx_curr_coalesce_frames = rx_frames; + pUmDevice->rx_curr_coalesce_ticks = rx_ticks; + pUmDevice->tx_curr_coalesce_frames = tx_frames; + pUmDevice->rx_curr_coalesce_frames_intr = rx_frames_intr; + REG_WR(pDevice, HostCoalesce.RxMaxCoalescedFrames, rx_frames); + + REG_WR(pDevice, HostCoalesce.RxCoalescingTicks, rx_ticks); + + REG_WR(pDevice, HostCoalesce.TxMaxCoalescedFrames, tx_frames); + + REG_WR(pDevice, HostCoalesce.RxMaxCoalescedFramesDuringInt, + rx_frames_intr); + + BCM5700_UNLOCK(pUmDevice, flags); + return 0; +} + +STATIC int +bcm5700_adapt_coalesce(PUM_DEVICE_BLOCK pUmDevice) +{ + PLM_DEVICE_BLOCK pDevice = &pUmDevice->lm_dev; + uint rx_curr_cnt, tx_curr_cnt, rx_delta, tx_delta, total_delta; + + rx_curr_cnt = pDevice->pStatsBlkVirt->ifHCInUcastPkts.Low; + tx_curr_cnt = pDevice->pStatsBlkVirt->ifHCOutUcastPkts.Low; + if ((rx_curr_cnt <= pUmDevice->rx_last_cnt) || + (tx_curr_cnt < pUmDevice->tx_last_cnt)) { + + /* skip if there is counter rollover */ + pUmDevice->rx_last_cnt = rx_curr_cnt; + pUmDevice->tx_last_cnt = tx_curr_cnt; + return 0; + } + + rx_delta = rx_curr_cnt - pUmDevice->rx_last_cnt; + tx_delta = tx_curr_cnt - pUmDevice->tx_last_cnt; + total_delta = (((rx_delta + rx_delta) + tx_delta) / 3) << 1; + + pUmDevice->rx_last_cnt = rx_curr_cnt; + pUmDevice->tx_last_cnt = tx_curr_cnt; + + if (total_delta < ADAPTIVE_LO_PKT_THRESH) { + if (pUmDevice->rx_curr_coalesce_frames != + ADAPTIVE_LO_RX_MAX_COALESCED_FRAMES) { + + bcm5700_do_adapt_coalesce(pUmDevice, + ADAPTIVE_LO_RX_MAX_COALESCED_FRAMES, + ADAPTIVE_LO_RX_COALESCING_TICKS, + ADAPTIVE_LO_TX_MAX_COALESCED_FRAMES, + ADAPTIVE_LO_RX_MAX_COALESCED_FRAMES_DURING_INT); + } + } + else if (total_delta < ADAPTIVE_HI_PKT_THRESH) { + if (pUmDevice->rx_curr_coalesce_frames != + DEFAULT_RX_MAX_COALESCED_FRAMES) { + + bcm5700_do_adapt_coalesce(pUmDevice, + DEFAULT_RX_MAX_COALESCED_FRAMES, + DEFAULT_RX_COALESCING_TICKS, + DEFAULT_TX_MAX_COALESCED_FRAMES, + DEFAULT_RX_MAX_COALESCED_FRAMES_DURING_INT); + } + } + else { + if (pUmDevice->rx_curr_coalesce_frames != + ADAPTIVE_HI_RX_MAX_COALESCED_FRAMES) { + + bcm5700_do_adapt_coalesce(pUmDevice, + ADAPTIVE_HI_RX_MAX_COALESCED_FRAMES, + ADAPTIVE_HI_RX_COALESCING_TICKS, + ADAPTIVE_HI_TX_MAX_COALESCED_FRAMES, + ADAPTIVE_HI_RX_MAX_COALESCED_FRAMES_DURING_INT); + } + } + return 0; +} +#endif +#endif + +STATIC void +bcm5700_reset(struct net_device *dev) +{ + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK)dev->priv; + PLM_DEVICE_BLOCK pDevice = (PLM_DEVICE_BLOCK) pUmDevice; + unsigned long flags; + + netif_stop_queue(dev); + bcm5700_intr_off(pUmDevice); + BCM5700_PHY_LOCK(pUmDevice, flags); + LM_ResetAdapter(pDevice); + pDevice->InitDone = TRUE; + bcm5700_set_vlan_mode(pUmDevice); + bcm5700_init_counters(pUmDevice); + if (memcmp(dev->dev_addr, pDevice->NodeAddress, 6)) { + LM_SetMacAddress(pDevice, dev->dev_addr); + } + BCM5700_PHY_UNLOCK(pUmDevice, flags); + atomic_set(&pUmDevice->intr_sem, 1); + bcm5700_intr_on(pUmDevice); + netif_wake_queue(dev); +} + +STATIC void +bcm5700_set_vlan_mode(UM_DEVICE_BLOCK *pUmDevice) +{ + LM_DEVICE_BLOCK *pDevice = &pUmDevice->lm_dev; + LM_UINT32 ReceiveMask = pDevice->ReceiveMask; + int vlan_tag_mode = pUmDevice->vlan_tag_mode; + + if (vlan_tag_mode == VLAN_TAG_MODE_AUTO_STRIP) { + if (pDevice->AsfFlags & ASF_ENABLED) { + vlan_tag_mode = VLAN_TAG_MODE_FORCED_STRIP; + } + else { + vlan_tag_mode = VLAN_TAG_MODE_NORMAL_STRIP; + } + } + if (vlan_tag_mode == VLAN_TAG_MODE_NORMAL_STRIP) { + ReceiveMask |= LM_KEEP_VLAN_TAG; +#ifdef BCM_VLAN + if (pUmDevice->vlgrp) + ReceiveMask &= ~LM_KEEP_VLAN_TAG; +#endif +#ifdef NICE_SUPPORT + if (pUmDevice->nice_rx) + ReceiveMask &= ~LM_KEEP_VLAN_TAG; +#endif + } + else if (vlan_tag_mode == VLAN_TAG_MODE_FORCED_STRIP) { + ReceiveMask &= ~LM_KEEP_VLAN_TAG; + } + if (ReceiveMask != pDevice->ReceiveMask) + { + LM_SetReceiveMask(pDevice, ReceiveMask); + } +} + +static void +bcm5700_poll_wait(UM_DEVICE_BLOCK *pUmDevice) +{ +#ifdef BCM_NAPI_RXPOLL + while (pUmDevice->lm_dev.RxPoll) { + current->state = TASK_INTERRUPTIBLE; + schedule_timeout(1); + } +#endif +} + + +#ifdef BCM_VLAN +STATIC void +bcm5700_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp) +{ + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) dev->priv; + + bcm5700_intr_off(pUmDevice); + bcm5700_poll_wait(pUmDevice); + pUmDevice->vlgrp = vlgrp; + bcm5700_set_vlan_mode(pUmDevice); + bcm5700_intr_on(pUmDevice); +} + +STATIC void +bcm5700_vlan_rx_kill_vid(struct net_device *dev, uint16_t vid) +{ + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) dev->priv; + + bcm5700_intr_off(pUmDevice); + bcm5700_poll_wait(pUmDevice); + if (pUmDevice->vlgrp) { + pUmDevice->vlgrp->vlan_devices[vid] = NULL; + } + bcm5700_intr_on(pUmDevice); +} +#endif + +STATIC int +bcm5700_start_xmit(struct sk_buff *skb, struct net_device *dev) +{ + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK)dev->priv; + PLM_DEVICE_BLOCK pDevice = (PLM_DEVICE_BLOCK) pUmDevice; + PLM_PACKET pPacket; + PUM_PACKET pUmPacket; + unsigned long flags = 0; + int frag_no; +#ifdef NICE_SUPPORT + vlan_tag_t *vlan_tag; +#endif +#ifdef BCM_TSO + LM_UINT32 mss; + uint16_t ip_tcp_len, tcp_opt_len, tcp_seg_flags; +#endif + + if ((pDevice->LinkStatus == LM_STATUS_LINK_DOWN) || + !pDevice->InitDone || pUmDevice->suspended) + { + dev_kfree_skb(skb); + return 0; + } + +#if (LINUX_VERSION_CODE < 0x02032b) + if (test_and_set_bit(0, &dev->tbusy)) { + return 1; + } +#endif + + if (pUmDevice->do_global_lock && pUmDevice->interrupt) { + netif_stop_queue(dev); + pUmDevice->tx_queued = 1; + if (!pUmDevice->interrupt) { + netif_wake_queue(dev); + pUmDevice->tx_queued = 0; + } + return 1; + } + + pPacket = (PLM_PACKET) + QQ_PopHead(&pDevice->TxPacketFreeQ.Container); + if (pPacket == 0) { + netif_stop_queue(dev); + pUmDevice->tx_full = 1; + if (QQ_GetEntryCnt(&pDevice->TxPacketFreeQ.Container)) { + netif_wake_queue(dev); + pUmDevice->tx_full = 0; + } + return 1; + } + pUmPacket = (PUM_PACKET) pPacket; + pUmPacket->skbuff = skb; + + if (skb->ip_summed == CHECKSUM_HW) { + pPacket->Flags = SND_BD_FLAG_TCP_UDP_CKSUM; +#if TIGON3_DEBUG + pUmDevice->tx_chksum_count++; +#endif + } + else { + pPacket->Flags = 0; + } +#if MAX_SKB_FRAGS + frag_no = skb_shinfo(skb)->nr_frags; +#else + frag_no = 0; +#endif + if (atomic_read(&pDevice->SendBdLeft) < (frag_no + 1)) { + netif_stop_queue(dev); + pUmDevice->tx_full = 1; + QQ_PushHead(&pDevice->TxPacketFreeQ.Container, pPacket); + if (atomic_read(&pDevice->SendBdLeft) >= (frag_no + 1)) { + netif_wake_queue(dev); + pUmDevice->tx_full = 0; + } + return 1; + } + + pPacket->u.Tx.FragCount = frag_no + 1; +#if TIGON3_DEBUG + if (pPacket->u.Tx.FragCount > 1) + pUmDevice->tx_zc_count++; +#endif + +#ifdef BCM_VLAN + if (pUmDevice->vlgrp && vlan_tx_tag_present(skb)) { + pPacket->VlanTag = vlan_tx_tag_get(skb); + pPacket->Flags |= SND_BD_FLAG_VLAN_TAG; + } +#endif +#ifdef NICE_SUPPORT + vlan_tag = (vlan_tag_t *) &skb->cb[0]; + if (vlan_tag->signature == 0x5555) { + pPacket->VlanTag = vlan_tag->tag; + pPacket->Flags |= SND_BD_FLAG_VLAN_TAG; + vlan_tag->signature = 0; + } +#endif + +#ifdef BCM_TSO + if ((mss = (LM_UINT32) skb_shinfo(skb)->tso_size) && + (skb->len > pDevice->TxMtu)) { + + pUmDevice->tso_pkt_count++; + + pPacket->Flags |= SND_BD_FLAG_CPU_PRE_DMA | + SND_BD_FLAG_CPU_POST_DMA; + + tcp_opt_len = 0; + if (skb->h.th->doff > 5) { + tcp_opt_len = (skb->h.th->doff - 5) << 2; + } + ip_tcp_len = (skb->nh.iph->ihl << 2) + sizeof(struct tcphdr); + skb->nh.iph->check = 0; + + if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5750) { + skb->h.th->check = 0; + pPacket->Flags &= ~SND_BD_FLAG_TCP_UDP_CKSUM; + } + else { + skb->h.th->check = ~csum_tcpudp_magic( + skb->nh.iph->saddr, skb->nh.iph->daddr, + 0, IPPROTO_TCP, 0); + } + + skb->nh.iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len); + tcp_seg_flags = 0; + if (tcp_opt_len || (skb->nh.iph->ihl > 5)) { + if (T3_ASIC_5705_OR_5750(pDevice->ChipRevId)) { + tcp_seg_flags = + ((skb->nh.iph->ihl - 5) + + (tcp_opt_len >> 2)) << 11; + } + else { + pPacket->Flags |= + ((skb->nh.iph->ihl - 5) + + (tcp_opt_len >> 2)) << 12; + } + } + pPacket->u.Tx.MaxSegmentSize = mss | tcp_seg_flags; + } + else + { + pPacket->u.Tx.MaxSegmentSize = 0; + } +#endif + BCM5700_LOCK(pUmDevice, flags); + LM_SendPacket(pDevice, pPacket); + BCM5700_UNLOCK(pUmDevice, flags); + +#if (LINUX_VERSION_CODE < 0x02032b) + netif_wake_queue(dev); +#endif + dev->trans_start = jiffies; + return 0; +} + +#ifdef BCM_NAPI_RXPOLL +STATIC int +bcm5700_poll(struct net_device *dev, int *budget) +{ + int orig_budget = *budget; + int work_done; + UM_DEVICE_BLOCK *pUmDevice = (UM_DEVICE_BLOCK *) dev->priv; + LM_DEVICE_BLOCK *pDevice = &pUmDevice->lm_dev; + unsigned long flags = 0; + LM_UINT32 tag; + + if (orig_budget > dev->quota) + orig_budget = dev->quota; + + BCM5700_LOCK(pUmDevice, flags); + work_done = LM_ServiceRxPoll(pDevice, orig_budget); + *budget -= work_done; + dev->quota -= work_done; + + if (QQ_GetEntryCnt(&pUmDevice->rx_out_of_buf_q.Container)) { + replenish_rx_buffers(pUmDevice, 0); + } + BCM5700_UNLOCK(pUmDevice, flags); + if (work_done) { + MM_IndicateRxPackets(pDevice); + BCM5700_LOCK(pUmDevice, flags); + LM_QueueRxPackets(pDevice); + BCM5700_UNLOCK(pUmDevice, flags); + } + if ((work_done < orig_budget) || atomic_read(&pUmDevice->intr_sem) || + pUmDevice->suspended) { + + netif_rx_complete(dev); + BCM5700_LOCK(pUmDevice, flags); + REG_WR(pDevice, Grc.Mode, pDevice->GrcMode); + pDevice->RxPoll = FALSE; + if (pDevice->RxPoll) { + BCM5700_UNLOCK(pUmDevice, flags); + return 0; + } + /* Take care of possible missed rx interrupts */ + REG_RD_BACK(pDevice, Grc.Mode); /* flush the register write */ + tag = pDevice->pStatusBlkVirt->StatusTag; + if ((pDevice->pStatusBlkVirt->Status & STATUS_BLOCK_UPDATED) || + (pDevice->pStatusBlkVirt->Idx[0].RcvProdIdx != + pDevice->RcvRetConIdx)) { + + REG_WR(pDevice, HostCoalesce.Mode, + pDevice->CoalesceMode | HOST_COALESCE_ENABLE | + HOST_COALESCE_NOW); + } + /* If a new status block is pending in the WDMA state machine */ + /* before the register write to enable the rx interrupt, */ + /* the new status block may DMA with no interrupt. In this */ + /* scenario, the tag read above will be older than the tag in */ + /* the pending status block and writing the older tag will */ + /* cause interrupt to be generated. */ + else if (pDevice->Flags & USE_TAGGED_STATUS_FLAG) { + MB_REG_WR(pDevice, Mailbox.Interrupt[0].Low, + tag << 24); + /* Make sure we service tx in case some tx interrupts */ + /* are cleared */ + if (atomic_read(&pDevice->SendBdLeft) < + (T3_SEND_RCB_ENTRY_COUNT / 2)) { + REG_WR(pDevice, HostCoalesce.Mode, + pDevice->CoalesceMode | + HOST_COALESCE_ENABLE | + HOST_COALESCE_NOW); + } + } + BCM5700_UNLOCK(pUmDevice, flags); + return 0; + } + return 1; +} +#endif /* BCM_NAPI_RXPOLL */ + +STATIC irqreturn_t +bcm5700_interrupt(int irq, void *dev_instance, struct pt_regs *regs) +{ + struct net_device *dev = (struct net_device *)dev_instance; + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK)dev->priv; + PLM_DEVICE_BLOCK pDevice = (PLM_DEVICE_BLOCK) pUmDevice; + LM_UINT32 oldtag, newtag; + int i, max_intr_loop; +#ifdef BCM_TASKLET + int repl_buf_count; +#endif + unsigned int handled = 1; + + if (!pDevice->InitDone) { + handled = 0; + return IRQ_RETVAL(handled); + } + + bcm5700_intr_lock(pUmDevice); + if (atomic_read(&pUmDevice->intr_sem)) { + MB_REG_WR(pDevice, Mailbox.Interrupt[0].Low, 1); +#ifdef INCLUDE_5750_A0_FIX + if (pDevice->Flags & FLUSH_POSTED_WRITE_FLAG) { + MB_REG_RD(pDevice, Mailbox.Interrupt[0].Low); + } +#endif + bcm5700_intr_unlock(pUmDevice); + handled = 0; + return IRQ_RETVAL(handled); + } + + if (test_and_set_bit(0, (void*)&pUmDevice->interrupt)) { + printk(KERN_ERR "%s: Duplicate entry of the interrupt handler\n", + dev->name); + bcm5700_intr_unlock(pUmDevice); + handled = 0; + return IRQ_RETVAL(handled); + } + + if ((pDevice->pStatusBlkVirt->Status & STATUS_BLOCK_UPDATED) || + pUmDevice->adapter_just_inited || pUmDevice->intr_test || + (pUmDevice->spurious_int > 100)) + { + + pUmDevice->spurious_int = 0; + if (pUmDevice->intr_test) { + if (!(REG_RD(pDevice, PciCfg.PciState) & + T3_PCI_STATE_INTERRUPT_NOT_ACTIVE)) { + pUmDevice->intr_test_result = 1; + } + pUmDevice->intr_test = 0; + } +#ifdef BCM_NAPI_RXPOLL + max_intr_loop = 1; +#else + max_intr_loop = 50; +#endif + if (pDevice->Flags & USE_TAGGED_STATUS_FLAG) { + MB_REG_WR(pDevice, Mailbox.Interrupt[0].Low, 1); +#ifdef INCLUDE_5750_A0_FIX + if (pDevice->Flags & FLUSH_POSTED_WRITE_FLAG) { + MB_REG_RD(pDevice, Mailbox.Interrupt[0].Low); + } +#endif + oldtag = pDevice->pStatusBlkVirt->StatusTag; + + for (i = 0; ; i++) { + pDevice->pStatusBlkVirt->Status &= + ~STATUS_BLOCK_UPDATED; + + LM_ServiceInterrupts(pDevice); + newtag = pDevice->pStatusBlkVirt->StatusTag; + if ((newtag == oldtag) || (i > max_intr_loop)) { + MB_REG_WR(pDevice, + Mailbox.Interrupt[0].Low, + oldtag << 24); +#ifdef INCLUDE_5750_A0_FIX + if (pDevice->Flags & + FLUSH_POSTED_WRITE_FLAG) { + + MB_REG_RD(pDevice, + Mailbox.Interrupt[0].Low); + } +#endif + pDevice->LastTag = oldtag; + if (pDevice->Flags & UNDI_FIX_FLAG) { + REG_WR(pDevice, Grc.LocalCtrl, + pDevice->GrcLocalCtrl | 0x2); + } + break; + } + oldtag = newtag; + } + } + else { + i = 0; + do { + uint dummy; + + MB_REG_WR(pDevice, Mailbox.Interrupt[0].Low, 1); + pDevice->pStatusBlkVirt->Status &= + ~STATUS_BLOCK_UPDATED; + LM_ServiceInterrupts(pDevice); + MB_REG_WR(pDevice, Mailbox.Interrupt[0].Low, 0); + dummy = MB_REG_RD(pDevice, + Mailbox.Interrupt[0].Low); + i++; + } + while ((pDevice->pStatusBlkVirt->Status & + STATUS_BLOCK_UPDATED) && (i < max_intr_loop)); + if (pDevice->Flags & UNDI_FIX_FLAG) { + REG_WR(pDevice, Grc.LocalCtrl, + pDevice->GrcLocalCtrl | 0x2); + } + } + } + else { + pUmDevice->spurious_int++; + handled = 0; + } +#ifdef BCM_TASKLET + repl_buf_count = QQ_GetEntryCnt(&pUmDevice->rx_out_of_buf_q.Container); + if (((repl_buf_count > pUmDevice->rx_buf_repl_panic_thresh) || + pDevice->QueueAgain) && + (!test_and_set_bit(0, &pUmDevice->tasklet_busy))) { + + replenish_rx_buffers(pUmDevice, + pUmDevice->rx_buf_repl_isr_limit); + clear_bit(0, (void*)&pUmDevice->tasklet_busy); + } + else if ((repl_buf_count > pUmDevice->rx_buf_repl_thresh) && + !pUmDevice->tasklet_pending) { + + pUmDevice->tasklet_pending = 1; + tasklet_schedule(&pUmDevice->tasklet); + } +#else +#ifdef BCM_NAPI_RXPOLL + if (!pDevice->RxPoll && + QQ_GetEntryCnt(&pUmDevice->rx_out_of_buf_q.Container)) { + pDevice->RxPoll = 1; + MM_ScheduleRxPoll(pDevice); + } +#else + if (QQ_GetEntryCnt(&pUmDevice->rx_out_of_buf_q.Container)) { + replenish_rx_buffers(pUmDevice, 0); + } + + if (QQ_GetEntryCnt(&pDevice->RxPacketFreeQ.Container) || + pDevice->QueueAgain) { + + LM_QueueRxPackets(pDevice); + } +#endif +#endif + + clear_bit(0, (void*)&pUmDevice->interrupt); + bcm5700_intr_unlock(pUmDevice); + if (pUmDevice->tx_queued) { + pUmDevice->tx_queued = 0; + netif_wake_queue(dev); + } + return IRQ_RETVAL(handled); +} + + +#ifdef BCM_TASKLET +STATIC void +bcm5700_tasklet(unsigned long data) +{ + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK)data; + unsigned long flags = 0; + + /* RH 7.2 Beta 3 tasklets are reentrant */ + if (test_and_set_bit(0, &pUmDevice->tasklet_busy)) { + pUmDevice->tasklet_pending = 0; + return; + } + + pUmDevice->tasklet_pending = 0; + if (pUmDevice->opened && !pUmDevice->suspended) { + BCM5700_LOCK(pUmDevice, flags); + replenish_rx_buffers(pUmDevice, 0); + BCM5700_UNLOCK(pUmDevice, flags); + } + + clear_bit(0, &pUmDevice->tasklet_busy); +} +#endif + +STATIC int +bcm5700_close(struct net_device *dev) +{ + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK)dev->priv; + PLM_DEVICE_BLOCK pDevice = (PLM_DEVICE_BLOCK) pUmDevice; + +#if (LINUX_VERSION_CODE < 0x02032b) + dev->start = 0; +#endif + netif_stop_queue(dev); + pUmDevice->opened = 0; + + if (tigon3_debug > 1) + printk(KERN_DEBUG "%s: Shutting down Tigon3\n", + dev->name); + + LM_MulticastClear(pDevice); + bcm5700_shutdown(pUmDevice); + del_timer(&pUmDevice->timer); + + free_irq(dev->irq, dev); +#if (LINUX_VERSION_CODE < 0x020300) + MOD_DEC_USE_COUNT; +#endif +#ifdef INCLUDE_5750_A0_FIX + if (!((pDevice->Flags & PCI_EXPRESS_FLAG) && + (pDevice->ChipRevId == T3_CHIP_ID_5750_A0))) +#endif + { + + LM_SetPowerState(pDevice, LM_POWER_STATE_D3); + } + bcm5700_freemem(dev); + + return 0; +} + +STATIC int +bcm5700_freemem(struct net_device *dev) +{ + int i; + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK)dev->priv; + + for (i = 0; i < pUmDevice->mem_list_num; i++) { + if (pUmDevice->mem_size_list[i] == 0) { + kfree(pUmDevice->mem_list[i]); + } + else { + pci_free_consistent(pUmDevice->pdev, + (size_t) pUmDevice->mem_size_list[i], + pUmDevice->mem_list[i], + pUmDevice->dma_list[i]); + } + } + pUmDevice->mem_list_num = 0; + +#ifdef NICE_SUPPORT + if (!pUmDevice->opened) { + for (i = 0; i < MAX_MEM2; i++) { + if (pUmDevice->mem_size_list2[i]) { + bcm5700_freemem2(pUmDevice, i); + } + } + } +#endif + return 0; +} + +#ifdef NICE_SUPPORT +/* Frees consistent memory allocated through ioctl */ +/* The memory to be freed is in mem_list2[index] */ +STATIC int +bcm5700_freemem2(UM_DEVICE_BLOCK *pUmDevice, int index) +{ +#if (LINUX_VERSION_CODE >= 0x020400) + void *ptr; + struct page *pg, *last_pg; + + /* Probably won't work on some architectures */ + ptr = pUmDevice->mem_list2[index], + pg = virt_to_page(ptr); + last_pg = virt_to_page(ptr + pUmDevice->mem_size_list2[index] - 1); + for (; ; pg++) { +#if (LINUX_VERSION_CODE > 0x020500) + ClearPageReserved(pg); +#else + mem_map_unreserve(pg); +#endif + if (pg == last_pg) + break; + } + pci_free_consistent(pUmDevice->pdev, + (size_t) pUmDevice->mem_size_list2[index], + pUmDevice->mem_list2[index], + pUmDevice->dma_list2[index]); + pUmDevice->mem_size_list2[index] = 0; +#endif + return 0; +} +#endif + +uint64_t +bcm5700_crc_count(PUM_DEVICE_BLOCK pUmDevice) +{ + PLM_DEVICE_BLOCK pDevice = &pUmDevice->lm_dev; + LM_UINT32 Value32; + PT3_STATS_BLOCK pStats = (PT3_STATS_BLOCK) pDevice->pStatsBlkVirt; + unsigned long flags; + + if ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || + T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) && + !(pDevice->TbiFlags & ENABLE_TBI_FLAG)) { + + if (!pUmDevice->opened || !pDevice->InitDone || + pUmDevice->adapter_just_inited) { + + return 0; + } + + /* regulate MDIO access during run time */ + if (pUmDevice->crc_counter_expiry > 0) + return pUmDevice->phy_crc_count; + + pUmDevice->crc_counter_expiry = (5 * HZ) / + pUmDevice->timer_interval; + + BCM5700_PHY_LOCK(pUmDevice, flags); + LM_ReadPhy(pDevice, 0x1e, &Value32); + if ((Value32 & 0x8000) == 0) + LM_WritePhy(pDevice, 0x1e, Value32 | 0x8000); + LM_ReadPhy(pDevice, 0x14, &Value32); + BCM5700_PHY_UNLOCK(pUmDevice, flags); + /* Sometimes data on the MDIO bus can be corrupted */ + if (Value32 != 0xffff) + pUmDevice->phy_crc_count += Value32; + return pUmDevice->phy_crc_count; + } + else if (pStats == 0) { + return 0; + } + else { + return (MM_GETSTATS64(pStats->dot3StatsFCSErrors)); + } +} + +uint64_t +bcm5700_rx_err_count(UM_DEVICE_BLOCK *pUmDevice) +{ + LM_DEVICE_BLOCK *pDevice = &pUmDevice->lm_dev; + T3_STATS_BLOCK *pStats = (T3_STATS_BLOCK *) pDevice->pStatsBlkVirt; + + if (pStats == 0) + return 0; + return (bcm5700_crc_count(pUmDevice) + + MM_GETSTATS64(pStats->dot3StatsAlignmentErrors) + + MM_GETSTATS64(pStats->etherStatsUndersizePkts) + + MM_GETSTATS64(pStats->etherStatsFragments) + + MM_GETSTATS64(pStats->dot3StatsFramesTooLong) + + MM_GETSTATS64(pStats->etherStatsJabbers)); +} + +STATIC struct net_device_stats * +bcm5700_get_stats(struct net_device *dev) +{ + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK)dev->priv; + PLM_DEVICE_BLOCK pDevice = (PLM_DEVICE_BLOCK) pUmDevice; + PT3_STATS_BLOCK pStats = (PT3_STATS_BLOCK) pDevice->pStatsBlkVirt; + struct net_device_stats *p_netstats = &pUmDevice->stats; + + if (pStats == 0) + return p_netstats; + + /* Get stats from LM */ + p_netstats->rx_packets = + MM_GETSTATS(pStats->ifHCInUcastPkts) + + MM_GETSTATS(pStats->ifHCInMulticastPkts) + + MM_GETSTATS(pStats->ifHCInBroadcastPkts); + p_netstats->tx_packets = + MM_GETSTATS(pStats->ifHCOutUcastPkts) + + MM_GETSTATS(pStats->ifHCOutMulticastPkts) + + MM_GETSTATS(pStats->ifHCOutBroadcastPkts); + p_netstats->rx_bytes = MM_GETSTATS(pStats->ifHCInOctets); + p_netstats->tx_bytes = MM_GETSTATS(pStats->ifHCOutOctets); + p_netstats->tx_errors = + MM_GETSTATS(pStats->dot3StatsInternalMacTransmitErrors) + + MM_GETSTATS(pStats->dot3StatsCarrierSenseErrors) + + MM_GETSTATS(pStats->ifOutDiscards) + + MM_GETSTATS(pStats->ifOutErrors); + p_netstats->multicast = MM_GETSTATS(pStats->ifHCInMulticastPkts); + p_netstats->collisions = MM_GETSTATS(pStats->etherStatsCollisions); + p_netstats->rx_length_errors = + MM_GETSTATS(pStats->dot3StatsFramesTooLong) + + MM_GETSTATS(pStats->etherStatsUndersizePkts); + p_netstats->rx_over_errors = MM_GETSTATS(pStats->nicNoMoreRxBDs); + p_netstats->rx_frame_errors = + MM_GETSTATS(pStats->dot3StatsAlignmentErrors); + p_netstats->rx_crc_errors = (unsigned long) + bcm5700_crc_count(pUmDevice); + p_netstats->rx_errors = (unsigned long) + bcm5700_rx_err_count(pUmDevice); + + p_netstats->tx_aborted_errors = MM_GETSTATS(pStats->ifOutDiscards); + p_netstats->tx_carrier_errors = + MM_GETSTATS(pStats->dot3StatsCarrierSenseErrors); + + return p_netstats; +} + +void +b57_suspend_chip(UM_DEVICE_BLOCK *pUmDevice) +{ + LM_DEVICE_BLOCK *pDevice = &pUmDevice->lm_dev; + + if (pUmDevice->opened) { + bcm5700_intr_off(pUmDevice); + netif_carrier_off(pUmDevice->dev); + netif_stop_queue(pUmDevice->dev); +#ifdef BCM_TASKLET + tasklet_kill(&pUmDevice->tasklet); +#endif + bcm5700_poll_wait(pUmDevice); + } + pUmDevice->suspended = 1; + LM_ShutdownChip(pDevice, LM_SUSPEND_RESET); +} + +void +b57_resume_chip(UM_DEVICE_BLOCK *pUmDevice) +{ + LM_DEVICE_BLOCK *pDevice = &pUmDevice->lm_dev; + + if (pUmDevice->suspended) { + pUmDevice->suspended = 0; + if (pUmDevice->opened) { + bcm5700_reset(pUmDevice->dev); + } + else { + LM_ShutdownChip(pDevice, LM_SHUTDOWN_RESET); + } + } +} + +/* Returns 0 on failure, 1 on success */ +int +b57_test_intr(UM_DEVICE_BLOCK *pUmDevice) +{ + LM_DEVICE_BLOCK *pDevice = &pUmDevice->lm_dev; + int j; + + if (!pUmDevice->opened) + return 0; + pUmDevice->intr_test_result = 0; + pUmDevice->intr_test = 1; + REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl | + GRC_MISC_LOCAL_CTRL_SET_INT); + for (j = 0; j < 10; j++) { + if (pUmDevice->intr_test_result) + break; + REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl | + GRC_MISC_LOCAL_CTRL_SET_INT); + MM_Sleep(pDevice, 1); + } + return pUmDevice->intr_test_result; +} + +#ifdef SIOCETHTOOL + +#ifdef ETHTOOL_GSTRINGS + +#define ETH_NUM_STATS 30 +#define RX_CRC_IDX 5 +#define RX_MAC_ERR_IDX 14 + +struct { + char string[ETH_GSTRING_LEN]; +} bcm5700_stats_str_arr[ETH_NUM_STATS] = { + { "rx_unicast_packets" }, + { "rx_multicast_packets" }, + { "rx_broadcast_packets" }, + { "rx_bytes" }, + { "rx_fragments" }, + { "rx_crc_errors" }, /* this needs to be calculated */ + { "rx_align_errors" }, + { "rx_xon_frames" }, + { "rx_xoff_frames" }, + { "rx_long_frames" }, + { "rx_short_frames" }, + { "rx_jabber" }, + { "rx_discards" }, + { "rx_errors" }, + { "rx_mac_errors" }, /* this needs to be calculated */ + { "tx_unicast_packets" }, + { "tx_multicast_packets" }, + { "tx_broadcast_packets" }, + { "tx_bytes" }, + { "tx_deferred" }, + { "tx_single_collisions" }, + { "tx_multi_collisions" }, + { "tx_total_collisions" }, + { "tx_excess_collisions" }, + { "tx_late_collisions" }, + { "tx_xon_frames" }, + { "tx_xoff_frames" }, + { "tx_internal_mac_errors" }, + { "tx_carrier_errors" }, + { "tx_errors" }, +}; + +#define STATS_OFFSET(offset_name) ((OFFSETOF(T3_STATS_BLOCK, offset_name)) / sizeof(uint64_t)) + +#ifdef __BIG_ENDIAN +#define SWAP_DWORD_64(x) (x) +#else +#define SWAP_DWORD_64(x) ((x << 32) | (x >> 32)) +#endif + +unsigned long bcm5700_stats_offset_arr[ETH_NUM_STATS] = { + STATS_OFFSET(ifHCInUcastPkts), + STATS_OFFSET(ifHCInMulticastPkts), + STATS_OFFSET(ifHCInBroadcastPkts), + STATS_OFFSET(ifHCInOctets), + STATS_OFFSET(etherStatsFragments), + 0, + STATS_OFFSET(dot3StatsAlignmentErrors), + STATS_OFFSET(xonPauseFramesReceived), + STATS_OFFSET(xoffPauseFramesReceived), + STATS_OFFSET(dot3StatsFramesTooLong), + STATS_OFFSET(etherStatsUndersizePkts), + STATS_OFFSET(etherStatsJabbers), + STATS_OFFSET(ifInDiscards), + STATS_OFFSET(ifInErrors), + 0, + STATS_OFFSET(ifHCOutUcastPkts), + STATS_OFFSET(ifHCOutMulticastPkts), + STATS_OFFSET(ifHCOutBroadcastPkts), + STATS_OFFSET(ifHCOutOctets), + STATS_OFFSET(dot3StatsDeferredTransmissions), + STATS_OFFSET(dot3StatsSingleCollisionFrames), + STATS_OFFSET(dot3StatsMultipleCollisionFrames), + STATS_OFFSET(etherStatsCollisions), + STATS_OFFSET(dot3StatsExcessiveCollisions), + STATS_OFFSET(dot3StatsLateCollisions), + STATS_OFFSET(outXonSent), + STATS_OFFSET(outXoffSent), + STATS_OFFSET(dot3StatsInternalMacTransmitErrors), + STATS_OFFSET(dot3StatsCarrierSenseErrors), + STATS_OFFSET(ifOutErrors), +}; + +#endif /* ETHTOOL_GSTRINGS */ + +#ifdef ETHTOOL_TEST +#define ETH_NUM_TESTS 6 +struct { + char string[ETH_GSTRING_LEN]; +} bcm5700_tests_str_arr[ETH_NUM_STATS] = { + { "register test (offline)" }, + { "memory test (offline)" }, + { "loopback test (offline)" }, + { "nvram test (online)" }, + { "interrupt test (online)" }, + { "link test (online)" }, +}; + +extern LM_STATUS b57_test_registers(UM_DEVICE_BLOCK *pUmDevice); +extern LM_STATUS b57_test_memory(UM_DEVICE_BLOCK *pUmDevice); +extern LM_STATUS b57_test_nvram(UM_DEVICE_BLOCK *pUmDevice); +extern LM_STATUS b57_test_link(UM_DEVICE_BLOCK *pUmDevice); +extern LM_STATUS b57_test_loopback(UM_DEVICE_BLOCK *pUmDevice); +#endif + +#ifdef ETHTOOL_GREGS +#if (LINUX_VERSION_CODE >= 0x02040f) +static void +bcm5700_get_reg_blk(UM_DEVICE_BLOCK *pUmDevice, u32 **buf, u32 start, u32 end, + int reserved) +{ + u32 offset; + LM_DEVICE_BLOCK *pDevice = &pUmDevice->lm_dev; + + if (reserved) { + memset(*buf, 0, end - start); + *buf = *buf + (end - start)/4; + return; + } + for (offset = start; offset < end; offset+=4, *buf = *buf + 1) { + if (T3_ASIC_5705_OR_5750(pDevice->ChipRevId)) { + if (((offset >= 0x3400) && (offset < 0x3c00)) || + ((offset >= 0x5400) && (offset < 0x5800)) || + ((offset >= 0x6400) && (offset < 0x6800))) { + **buf = 0; + continue; + } + } + **buf = REG_RD_OFFSET(pDevice, offset); + } +} +#endif +#endif + +static int netdev_ethtool_ioctl(struct net_device *dev, void *useraddr) +{ + struct ethtool_cmd ethcmd; + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK)dev->priv; + PLM_DEVICE_BLOCK pDevice = (PLM_DEVICE_BLOCK) pUmDevice; + + if (copy_from_user(ðcmd, useraddr, sizeof(ethcmd))) + return -EFAULT; + + switch (ethcmd.cmd) { +#ifdef ETHTOOL_GDRVINFO + case ETHTOOL_GDRVINFO: { + struct ethtool_drvinfo info = {ETHTOOL_GDRVINFO}; + + strcpy(info.driver, bcm5700_driver); +#if INCLUDE_5701_AX_FIX + if(pDevice->ChipRevId == T3_CHIP_ID_5701_A0) { + extern int t3FwReleaseMajor; + extern int t3FwReleaseMinor; + extern int t3FwReleaseFix; + + sprintf(info.fw_version, "%i.%i.%i", + t3FwReleaseMajor, t3FwReleaseMinor, + t3FwReleaseFix); + } +#endif + strcpy(info.version, bcm5700_version); + strcpy(info.bus_info, pUmDevice->pdev->slot_name); +#ifdef ETHTOOL_GEEPROM + BCM_EEDUMP_LEN(&info, pDevice->NvramSize); +#endif +#ifdef ETHTOOL_GREGS + /* dump everything, including holes in the register space */ + info.regdump_len = 0x6c00; +#endif +#ifdef ETHTOOL_GSTATS + info.n_stats = ETH_NUM_STATS; +#endif +#ifdef ETHTOOL_TEST + info.testinfo_len = ETH_NUM_TESTS; +#endif + if (copy_to_user(useraddr, &info, sizeof(info))) + return -EFAULT; + return 0; + } +#endif + case ETHTOOL_GSET: { + if (pDevice->TbiFlags & ENABLE_TBI_FLAG) { + ethcmd.supported = + (SUPPORTED_1000baseT_Full | + SUPPORTED_Autoneg); + ethcmd.supported |= SUPPORTED_FIBRE; + ethcmd.port = PORT_FIBRE; + } + else { + ethcmd.supported = + (SUPPORTED_10baseT_Half | + SUPPORTED_10baseT_Full | + SUPPORTED_100baseT_Half | + SUPPORTED_100baseT_Full | + SUPPORTED_1000baseT_Half | + SUPPORTED_1000baseT_Full | + SUPPORTED_Autoneg); + ethcmd.supported |= SUPPORTED_TP; + ethcmd.port = PORT_TP; + } + + ethcmd.transceiver = XCVR_INTERNAL; + ethcmd.phy_address = 0; + + if (pUmDevice->line_speed == 1000) + ethcmd.speed = SPEED_1000; + else if (pUmDevice->line_speed == 100) + ethcmd.speed = SPEED_100; + else if (pUmDevice->line_speed == 10) + ethcmd.speed = SPEED_10; + else + ethcmd.speed = 0; + + if (pDevice->DuplexMode == LM_DUPLEX_MODE_FULL) + ethcmd.duplex = DUPLEX_FULL; + else + ethcmd.duplex = DUPLEX_HALF; + + if (pDevice->DisableAutoNeg == FALSE) { + ethcmd.autoneg = AUTONEG_ENABLE; + ethcmd.advertising = ADVERTISED_Autoneg; + if (pDevice->TbiFlags & ENABLE_TBI_FLAG) { + ethcmd.advertising |= + ADVERTISED_1000baseT_Full | + ADVERTISED_FIBRE; + } + else { + ethcmd.advertising |= + ADVERTISED_TP; + if (pDevice->advertising & + PHY_AN_AD_10BASET_HALF) { + + ethcmd.advertising |= + ADVERTISED_10baseT_Half; + } + if (pDevice->advertising & + PHY_AN_AD_10BASET_FULL) { + + ethcmd.advertising |= + ADVERTISED_10baseT_Full; + } + if (pDevice->advertising & + PHY_AN_AD_100BASETX_HALF) { + + ethcmd.advertising |= + ADVERTISED_100baseT_Half; + } + if (pDevice->advertising & + PHY_AN_AD_100BASETX_FULL) { + + ethcmd.advertising |= + ADVERTISED_100baseT_Full; + } + if (pDevice->advertising1000 & + BCM540X_AN_AD_1000BASET_HALF) { + + ethcmd.advertising |= + ADVERTISED_1000baseT_Half; + } + if (pDevice->advertising1000 & + BCM540X_AN_AD_1000BASET_FULL) { + + ethcmd.advertising |= + ADVERTISED_1000baseT_Full; + } + } + } + else { + ethcmd.autoneg = AUTONEG_DISABLE; + ethcmd.advertising = 0; + } + + ethcmd.maxtxpkt = pDevice->TxMaxCoalescedFrames; + ethcmd.maxrxpkt = pDevice->RxMaxCoalescedFrames; + + if(copy_to_user(useraddr, ðcmd, sizeof(ethcmd))) + return -EFAULT; + return 0; + } + case ETHTOOL_SSET: { + unsigned long flags; + + if(!capable(CAP_NET_ADMIN)) + return -EPERM; + if (ethcmd.autoneg == AUTONEG_ENABLE) { + pDevice->RequestedLineSpeed = LM_LINE_SPEED_AUTO; + pDevice->RequestedDuplexMode = LM_DUPLEX_MODE_UNKNOWN; + pDevice->DisableAutoNeg = FALSE; + } + else { + if (ethcmd.speed == SPEED_1000) { + if (!(pDevice->TbiFlags & ENABLE_TBI_FLAG) || + (pDevice->PhyFlags & PHY_NO_GIGABIT)) + return -EINVAL; + + pDevice->RequestedLineSpeed = + LM_LINE_SPEED_1000MBPS; + + pDevice->RequestedDuplexMode = + LM_DUPLEX_MODE_FULL; + } + else if (ethcmd.speed == SPEED_100) { + pDevice->RequestedLineSpeed = + LM_LINE_SPEED_100MBPS; + } + else if (ethcmd.speed == SPEED_10) { + pDevice->RequestedLineSpeed = + LM_LINE_SPEED_10MBPS; + } + else { + return -EINVAL; + } + + pDevice->DisableAutoNeg = TRUE; + if (ethcmd.duplex == DUPLEX_FULL) { + pDevice->RequestedDuplexMode = + LM_DUPLEX_MODE_FULL; + } + else { + pDevice->RequestedDuplexMode = + LM_DUPLEX_MODE_HALF; + } + } + BCM5700_PHY_LOCK(pUmDevice, flags); + LM_SetupPhy(pDevice); + BCM5700_PHY_UNLOCK(pUmDevice, flags); + return 0; + } +#ifdef ETHTOOL_GWOL +#ifdef BCM_WOL + case ETHTOOL_GWOL: { + struct ethtool_wolinfo wol = {ETHTOOL_GWOL}; + + if (((pDevice->TbiFlags & ENABLE_TBI_FLAG) && + !(pDevice->Flags & FIBER_WOL_CAPABLE_FLAG)) || + (pDevice->Flags & DISABLE_D3HOT_FLAG)) { + wol.supported = 0; + wol.wolopts = 0; + } + else { + wol.supported = WAKE_MAGIC; + if (pDevice->WakeUpMode == LM_WAKE_UP_MODE_MAGIC_PACKET) + { + wol.wolopts = WAKE_MAGIC; + } + else { + wol.wolopts = 0; + } + } + if (copy_to_user(useraddr, &wol, sizeof(wol))) + return -EFAULT; + return 0; + } + case ETHTOOL_SWOL: { + struct ethtool_wolinfo wol; + + if(!capable(CAP_NET_ADMIN)) + return -EPERM; + if (copy_from_user(&wol, useraddr, sizeof(wol))) + return -EFAULT; + if ((((pDevice->TbiFlags & ENABLE_TBI_FLAG) && + !(pDevice->Flags & FIBER_WOL_CAPABLE_FLAG)) || + (pDevice->Flags & DISABLE_D3HOT_FLAG)) && + wol.wolopts) { + return -EINVAL; + } + + if ((wol.wolopts & ~WAKE_MAGIC) != 0) { + return -EINVAL; + } + if (wol.wolopts & WAKE_MAGIC) { + pDevice->WakeUpModeCap = LM_WAKE_UP_MODE_MAGIC_PACKET; + pDevice->WakeUpMode = LM_WAKE_UP_MODE_MAGIC_PACKET; + } + else { + pDevice->WakeUpModeCap = LM_WAKE_UP_MODE_NONE; + pDevice->WakeUpMode = LM_WAKE_UP_MODE_NONE; + } + return 0; + } +#endif +#endif +#ifdef ETHTOOL_GLINK + case ETHTOOL_GLINK: { + struct ethtool_value edata = {ETHTOOL_GLINK}; + + /* workaround for DHCP using ifup script */ + /* ifup only waits for 5 seconds for link up */ + /* NIC may take more than 5 seconds to establish link */ + if ((pUmDevice->delayed_link_ind > 0) && + delay_link[pUmDevice->index]) + return -EOPNOTSUPP; + + if (pDevice->LinkStatus == LM_STATUS_LINK_ACTIVE) { + edata.data = 1; + } + else { + edata.data = 0; + } + if (copy_to_user(useraddr, &edata, sizeof(edata))) + return -EFAULT; + return 0; + } +#endif +#ifdef ETHTOOL_NWAY_RST + case ETHTOOL_NWAY_RST: { + LM_UINT32 phyctrl; + unsigned long flags; + + if(!capable(CAP_NET_ADMIN)) + return -EPERM; + if (pDevice->DisableAutoNeg) { + return -EINVAL; + } + BCM5700_PHY_LOCK(pUmDevice, flags); + if (pDevice->TbiFlags & ENABLE_TBI_FLAG) { + pDevice->RequestedLineSpeed = LM_LINE_SPEED_1000MBPS; + pDevice->DisableAutoNeg = TRUE; + LM_SetupPhy(pDevice); + + pDevice->RequestedLineSpeed = LM_LINE_SPEED_AUTO; + pDevice->DisableAutoNeg = FALSE; + LM_SetupPhy(pDevice); + } + else { + if ((T3_ASIC_REV(pDevice->ChipRevId) == + T3_ASIC_REV_5703) || + (T3_ASIC_REV(pDevice->ChipRevId) == + T3_ASIC_REV_5704) || + (T3_ASIC_REV(pDevice->ChipRevId) == + T3_ASIC_REV_5705)) + { + LM_ResetPhy(pDevice); + LM_SetupPhy(pDevice); + } + LM_ReadPhy(pDevice, PHY_CTRL_REG, &phyctrl); + LM_WritePhy(pDevice, PHY_CTRL_REG, phyctrl | + PHY_CTRL_AUTO_NEG_ENABLE | + PHY_CTRL_RESTART_AUTO_NEG); + } + BCM5700_PHY_UNLOCK(pUmDevice, flags); + return 0; + } +#endif +#ifdef ETHTOOL_GEEPROM + case ETHTOOL_GEEPROM: { + struct ethtool_eeprom eeprom; + LM_UINT32 *buf = 0; + LM_UINT32 buf1[64/4]; + int i, j, offset, len; + + if (copy_from_user(&eeprom, useraddr, sizeof(eeprom))) + return -EFAULT; + + if (eeprom.offset >= pDevice->NvramSize) + return -EFAULT; + + /* maximum data limited */ + /* to read more, call again with a different offset */ + if (eeprom.len > 0x800) { + eeprom.len = 0x800; + if (copy_to_user(useraddr, &eeprom, sizeof(eeprom))) + return -EFAULT; + } + + if (eeprom.len > 64) { + buf = kmalloc(eeprom.len, GFP_KERNEL); + if (!buf) + return -ENOMEM; + } + else { + buf = buf1; + } + useraddr += offsetof(struct ethtool_eeprom, data); + + offset = eeprom.offset; + len = eeprom.len; + if (offset & 3) { + offset &= 0xfffffffc; + len += (offset & 3); + } + len = (len + 3) & 0xfffffffc; + for (i = 0, j = 0; j < len; i++, j += 4) { + if (LM_NvramRead(pDevice, offset + j, buf + i) != + LM_STATUS_SUCCESS) { + break; + } + } + if (j >= len) { + buf += (eeprom.offset & 3); + i = copy_to_user(useraddr, buf, eeprom.len); + } + if (eeprom.len > 64) { + kfree(buf); + } + if ((j < len) || i) + return -EFAULT; + return 0; + } + case ETHTOOL_SEEPROM: { + struct ethtool_eeprom eeprom; + LM_UINT32 buf[64/4]; + int i, offset, len; + + if(!capable(CAP_NET_ADMIN)) + return -EPERM; + if (copy_from_user(&eeprom, useraddr, sizeof(eeprom))) + return -EFAULT; + + if ((eeprom.offset & 3) || (eeprom.len & 3) || + (eeprom.offset >= pDevice->NvramSize)) { + return -EFAULT; + } + + if ((eeprom.offset + eeprom.len) >= pDevice->NvramSize) { + eeprom.len = pDevice->NvramSize - eeprom.offset; + } + + useraddr += offsetof(struct ethtool_eeprom, data); + + len = eeprom.len; + offset = eeprom.offset; + for (; len > 0; ) { + if (len < 64) + i = len; + else + i = 64; + if (copy_from_user(&buf, useraddr, i)) + return -EFAULT; + + bcm5700_intr_off(pUmDevice); + /* Prevent race condition on Grc.Mode register */ + bcm5700_poll_wait(pUmDevice); + + if (LM_NvramWriteBlock(pDevice, offset, buf, i/4) != + LM_STATUS_SUCCESS) { + bcm5700_intr_on(pUmDevice); + return -EFAULT; + } + bcm5700_intr_on(pUmDevice); + len -= i; + offset += i; + useraddr += i; + } + return 0; + } +#endif +#ifdef ETHTOOL_GREGS +#if (LINUX_VERSION_CODE >= 0x02040f) + case ETHTOOL_GREGS: { + struct ethtool_regs eregs; + LM_UINT32 *buf, *buf1; + unsigned int i; + + if(!capable(CAP_NET_ADMIN)) + return -EPERM; + if (pDevice->Flags & UNDI_FIX_FLAG) + return -EOPNOTSUPP; + if (copy_from_user(&eregs, useraddr, sizeof(eregs))) + return -EFAULT; + if (eregs.len > 0x6c00) + eregs.len = 0x6c00; + eregs.version = 0x0; + if (copy_to_user(useraddr, &eregs, sizeof(eregs))) + return -EFAULT; + buf = buf1 = kmalloc(eregs.len, GFP_KERNEL); + if (!buf) + return -ENOMEM; + bcm5700_get_reg_blk(pUmDevice, &buf, 0, 0xb0, 0); + bcm5700_get_reg_blk(pUmDevice, &buf, 0xb0, 0x200, 1); + bcm5700_get_reg_blk(pUmDevice, &buf, 0x200, 0x8f0, 0); + bcm5700_get_reg_blk(pUmDevice, &buf, 0x8f0, 0xc00, 1); + bcm5700_get_reg_blk(pUmDevice, &buf, 0xc00, 0xce0, 0); + bcm5700_get_reg_blk(pUmDevice, &buf, 0xce0, 0x1000, 1); + bcm5700_get_reg_blk(pUmDevice, &buf, 0x1000, 0x1004, 0); + bcm5700_get_reg_blk(pUmDevice, &buf, 0x1004, 0x1400, 1); + bcm5700_get_reg_blk(pUmDevice, &buf, 0x1400, 0x1480, 0); + bcm5700_get_reg_blk(pUmDevice, &buf, 0x1480, 0x1800, 1); + bcm5700_get_reg_blk(pUmDevice, &buf, 0x1800, 0x1848, 0); + bcm5700_get_reg_blk(pUmDevice, &buf, 0x1848, 0x1c00, 1); + bcm5700_get_reg_blk(pUmDevice, &buf, 0x1c00, 0x1c04, 0); + bcm5700_get_reg_blk(pUmDevice, &buf, 0x1c04, 0x2000, 1); + bcm5700_get_reg_blk(pUmDevice, &buf, 0x2000, 0x225c, 0); + bcm5700_get_reg_blk(pUmDevice, &buf, 0x225c, 0x2400, 1); + bcm5700_get_reg_blk(pUmDevice, &buf, 0x2400, 0x24c4, 0); + bcm5700_get_reg_blk(pUmDevice, &buf, 0x24c4, 0x2800, 1); + bcm5700_get_reg_blk(pUmDevice, &buf, 0x2800, 0x2804, 0); + bcm5700_get_reg_blk(pUmDevice, &buf, 0x2804, 0x2c00, 1); + bcm5700_get_reg_blk(pUmDevice, &buf, 0x2c00, 0x2c20, 0); + bcm5700_get_reg_blk(pUmDevice, &buf, 0x2c20, 0x3000, 1); + bcm5700_get_reg_blk(pUmDevice, &buf, 0x3000, 0x3014, 0); + bcm5700_get_reg_blk(pUmDevice, &buf, 0x3014, 0x3400, 1); + bcm5700_get_reg_blk(pUmDevice, &buf, 0x3400, 0x3408, 0); + bcm5700_get_reg_blk(pUmDevice, &buf, 0x3408, 0x3800, 1); + bcm5700_get_reg_blk(pUmDevice, &buf, 0x3800, 0x3808, 0); + bcm5700_get_reg_blk(pUmDevice, &buf, 0x3808, 0x3c00, 1); + bcm5700_get_reg_blk(pUmDevice, &buf, 0x3c00, 0x3d00, 0); + bcm5700_get_reg_blk(pUmDevice, &buf, 0x3d00, 0x4000, 1); + bcm5700_get_reg_blk(pUmDevice, &buf, 0x4000, 0x4010, 0); + bcm5700_get_reg_blk(pUmDevice, &buf, 0x4010, 0x4400, 1); + bcm5700_get_reg_blk(pUmDevice, &buf, 0x4400, 0x4458, 0); + bcm5700_get_reg_blk(pUmDevice, &buf, 0x4458, 0x4800, 1); + bcm5700_get_reg_blk(pUmDevice, &buf, 0x4800, 0x4808, 0); + bcm5700_get_reg_blk(pUmDevice, &buf, 0x4808, 0x4c00, 1); + bcm5700_get_reg_blk(pUmDevice, &buf, 0x4c00, 0x4c08, 0); + bcm5700_get_reg_blk(pUmDevice, &buf, 0x4c08, 0x5000, 1); + bcm5700_get_reg_blk(pUmDevice, &buf, 0x5000, 0x5050, 0); + bcm5700_get_reg_blk(pUmDevice, &buf, 0x5050, 0x5400, 1); + bcm5700_get_reg_blk(pUmDevice, &buf, 0x5400, 0x5450, 0); + bcm5700_get_reg_blk(pUmDevice, &buf, 0x5450, 0x5800, 1); + bcm5700_get_reg_blk(pUmDevice, &buf, 0x5800, 0x5a10, 0); + bcm5700_get_reg_blk(pUmDevice, &buf, 0x5a10, 0x6000, 1); + bcm5700_get_reg_blk(pUmDevice, &buf, 0x6000, 0x600c, 0); + bcm5700_get_reg_blk(pUmDevice, &buf, 0x600c, 0x6400, 1); + bcm5700_get_reg_blk(pUmDevice, &buf, 0x6400, 0x6404, 0); + bcm5700_get_reg_blk(pUmDevice, &buf, 0x6404, 0x6800, 1); + bcm5700_get_reg_blk(pUmDevice, &buf, 0x6800, 0x6848, 0); + bcm5700_get_reg_blk(pUmDevice, &buf, 0x6848, 0x6c00, 1); + + i = copy_to_user(useraddr + sizeof(eregs), buf1, eregs.len); + kfree(buf); + if (i) + return -EFAULT; + return 0; + } +#endif +#endif +#ifdef ETHTOOL_GPAUSEPARAM + case ETHTOOL_GPAUSEPARAM: { + struct ethtool_pauseparam epause = { ETHTOOL_GPAUSEPARAM }; + + if (!pDevice->DisableAutoNeg) { + epause.autoneg = (pDevice->FlowControlCap & + LM_FLOW_CONTROL_AUTO_PAUSE) != 0; + } + else { + epause.autoneg = 0; + } + epause.rx_pause = + (pDevice->FlowControl & + LM_FLOW_CONTROL_RECEIVE_PAUSE) != 0; + epause.tx_pause = + (pDevice->FlowControl & + LM_FLOW_CONTROL_TRANSMIT_PAUSE) != 0; + if (copy_to_user(useraddr, &epause, sizeof(epause))) + return -EFAULT; + + return 0; + } + case ETHTOOL_SPAUSEPARAM: { + struct ethtool_pauseparam epause; + unsigned long flags; + + if(!capable(CAP_NET_ADMIN)) + return -EPERM; + if (copy_from_user(&epause, useraddr, sizeof(epause))) + return -EFAULT; + pDevice->FlowControlCap = 0; + if (epause.autoneg && !pDevice->DisableAutoNeg) { + pDevice->FlowControlCap |= LM_FLOW_CONTROL_AUTO_PAUSE; + } + if (epause.rx_pause) { + pDevice->FlowControlCap |= + LM_FLOW_CONTROL_RECEIVE_PAUSE; + } + if (epause.tx_pause) { + pDevice->FlowControlCap |= + LM_FLOW_CONTROL_TRANSMIT_PAUSE; + } + BCM5700_PHY_LOCK(pUmDevice, flags); + LM_SetupPhy(pDevice); + BCM5700_PHY_UNLOCK(pUmDevice, flags); + + return 0; + } +#endif +#ifdef ETHTOOL_GRXCSUM + case ETHTOOL_GRXCSUM: { + struct ethtool_value edata = { ETHTOOL_GRXCSUM }; + + edata.data = + (pDevice->TaskToOffload & + LM_TASK_OFFLOAD_RX_TCP_CHECKSUM) != 0; + if (copy_to_user(useraddr, &edata, sizeof(edata))) + return -EFAULT; + + return 0; + } + case ETHTOOL_SRXCSUM: { + struct ethtool_value edata; + + if(!capable(CAP_NET_ADMIN)) + return -EPERM; + if (copy_from_user(&edata, useraddr, sizeof(edata))) + return -EFAULT; + if (edata.data) { + if (!(pDevice->TaskOffloadCap & + LM_TASK_OFFLOAD_TX_TCP_CHECKSUM)) { + + return -EINVAL; + } + pDevice->TaskToOffload |= + LM_TASK_OFFLOAD_RX_TCP_CHECKSUM | + LM_TASK_OFFLOAD_RX_UDP_CHECKSUM; + } + else { + pDevice->TaskToOffload &= + ~(LM_TASK_OFFLOAD_RX_TCP_CHECKSUM | + LM_TASK_OFFLOAD_RX_UDP_CHECKSUM); + } + return 0; + } + case ETHTOOL_GTXCSUM: { + struct ethtool_value edata = { ETHTOOL_GTXCSUM }; + + edata.data = + (dev->features & NETIF_F_IP_CSUM) != 0; + if (copy_to_user(useraddr, &edata, sizeof(edata))) + return -EFAULT; + + return 0; + } + case ETHTOOL_STXCSUM: { + struct ethtool_value edata; + + if(!capable(CAP_NET_ADMIN)) + return -EPERM; + if (copy_from_user(&edata, useraddr, sizeof(edata))) + return -EFAULT; + if (edata.data) { + if (!(pDevice->TaskOffloadCap & + LM_TASK_OFFLOAD_TX_TCP_CHECKSUM)) { + + return -EINVAL; + } + dev->features |= NETIF_F_IP_CSUM; + pDevice->TaskToOffload |= + LM_TASK_OFFLOAD_TX_TCP_CHECKSUM | + LM_TASK_OFFLOAD_TX_UDP_CHECKSUM; + } + else { + dev->features &= ~NETIF_F_IP_CSUM; + pDevice->TaskToOffload &= + ~(LM_TASK_OFFLOAD_TX_TCP_CHECKSUM | + LM_TASK_OFFLOAD_TX_UDP_CHECKSUM); + } + return 0; + } + case ETHTOOL_GSG: { + struct ethtool_value edata = { ETHTOOL_GSG }; + + edata.data = + (dev->features & NETIF_F_SG) != 0; + if (copy_to_user(useraddr, &edata, sizeof(edata))) + return -EFAULT; + return 0; + } + case ETHTOOL_SSG: { + struct ethtool_value edata; + + if(!capable(CAP_NET_ADMIN)) + return -EPERM; + if (copy_from_user(&edata, useraddr, sizeof(edata))) + return -EFAULT; + if (edata.data) { + dev->features |= NETIF_F_SG; + } + else { + dev->features &= ~NETIF_F_SG; + } + return 0; + } +#endif +#ifdef ETHTOOL_GRINGPARAM + case ETHTOOL_GRINGPARAM: { + struct ethtool_ringparam ering = { ETHTOOL_GRINGPARAM }; + + ering.rx_max_pending = T3_STD_RCV_RCB_ENTRY_COUNT - 1; + ering.rx_pending = pDevice->RxStdDescCnt; + ering.rx_mini_max_pending = 0; + ering.rx_mini_pending = 0; +#if T3_JUMBO_RCV_RCB_ENTRY_COUNT + ering.rx_jumbo_max_pending = T3_JUMBO_RCV_RCB_ENTRY_COUNT - 1; + ering.rx_jumbo_pending = pDevice->RxJumboDescCnt; +#else + ering.rx_jumbo_max_pending = 0; + ering.rx_jumbo_pending = 0; +#endif + ering.tx_max_pending = MAX_TX_PACKET_DESC_COUNT - 1; + ering.tx_pending = pDevice->TxPacketDescCnt; + if (copy_to_user(useraddr, &ering, sizeof(ering))) + return -EFAULT; + return 0; + } +#endif +#ifdef ETHTOOL_PHYS_ID + case ETHTOOL_PHYS_ID: { + struct ethtool_value edata; + + if(!capable(CAP_NET_ADMIN)) + return -EPERM; + if (copy_from_user(&edata, useraddr, sizeof(edata))) + return -EFAULT; + if (LM_BlinkLED(pDevice, edata.data) == LM_STATUS_SUCCESS) + return 0; + return -EINTR; + } +#endif +#ifdef ETHTOOL_GSTRINGS + case ETHTOOL_GSTRINGS: { + struct ethtool_gstrings egstr = { ETHTOOL_GSTRINGS }; + + if (copy_from_user(&egstr, useraddr, sizeof(egstr))) + return -EFAULT; + switch(egstr.string_set) { +#ifdef ETHTOOL_GSTATS + case ETH_SS_STATS: + egstr.len = ETH_NUM_STATS; + if (copy_to_user(useraddr, &egstr, sizeof(egstr))) + return -EFAULT; + if (copy_to_user(useraddr + sizeof(egstr), + bcm5700_stats_str_arr, + sizeof(bcm5700_stats_str_arr))) + return -EFAULT; + return 0; +#endif +#ifdef ETHTOOL_TEST + case ETH_SS_TEST: + egstr.len = ETH_NUM_TESTS; + if (copy_to_user(useraddr, &egstr, sizeof(egstr))) + return -EFAULT; + if (copy_to_user(useraddr + sizeof(egstr), + bcm5700_tests_str_arr, + sizeof(bcm5700_tests_str_arr))) + return -EFAULT; + return 0; +#endif + default: + return -EOPNOTSUPP; + } + } +#endif +#ifdef ETHTOOL_GSTATS + case ETHTOOL_GSTATS: { + struct ethtool_stats estats = { ETHTOOL_GSTATS }; + uint64_t stats[ETH_NUM_STATS]; + int i; + uint64_t *pStats = + (uint64_t *) pDevice->pStatsBlkVirt; + + estats.n_stats = ETH_NUM_STATS; + if (pStats == 0) { + memset(stats, 0, sizeof(stats)); + } + else { + + for (i = 0; i < ETH_NUM_STATS; i++) { + if (bcm5700_stats_offset_arr[i] != 0) { + stats[i] = SWAP_DWORD_64(*(pStats + + bcm5700_stats_offset_arr[i])); + } + else if (i == RX_CRC_IDX) { + stats[i] = + bcm5700_crc_count(pUmDevice); + } + else if (i == RX_MAC_ERR_IDX) { + stats[i] = + bcm5700_rx_err_count(pUmDevice); + } + } + } + if (copy_to_user(useraddr, &estats, sizeof(estats))) { + return -EFAULT; + } + if (copy_to_user(useraddr + sizeof(estats), &stats, + sizeof(stats))) { + return -EFAULT; + } + return 0; + } +#endif +#ifdef ETHTOOL_TEST + case ETHTOOL_TEST: { + struct ethtool_test etest; + uint64_t tests[ETH_NUM_TESTS] = {0, 0, 0, 0, 0, 0}; + LM_POWER_STATE old_power_level; + + if (copy_from_user(&etest, useraddr, sizeof(etest))) + return -EFAULT; + + etest.len = ETH_NUM_TESTS; + old_power_level = pDevice->PowerLevel; + if (old_power_level != LM_POWER_STATE_D0) { + LM_SetPowerState(pDevice, LM_POWER_STATE_D0); + LM_SwitchClocks(pDevice); + } + if (etest.flags & ETH_TEST_FL_OFFLINE) { + b57_suspend_chip(pUmDevice); + LM_HaltCpu(pDevice,T3_RX_CPU_ID); + if (!T3_ASIC_5705_OR_5750(pDevice->ChipRevId)) { + LM_HaltCpu(pDevice,T3_TX_CPU_ID); + } + if (b57_test_registers(pUmDevice) == 0) { + etest.flags |= ETH_TEST_FL_FAILED; + tests[0] = 1; + } + if (b57_test_memory(pUmDevice) == 0) { + etest.flags |= ETH_TEST_FL_FAILED; + tests[1] = 1; + } + if (b57_test_loopback(pUmDevice) == 0) { + etest.flags |= ETH_TEST_FL_FAILED; + tests[2] = 1; + } + b57_resume_chip(pUmDevice); + /* wait for link to come up for the link test */ + MM_Sleep(pDevice, 4000); + if ((pDevice->LinkStatus != LM_STATUS_LINK_ACTIVE) && + !(pDevice->TbiFlags & ENABLE_TBI_FLAG)) { + + /* wait a little longer for linkup on copper */ + MM_Sleep(pDevice, 3000); + } + } + if (b57_test_nvram(pUmDevice) == 0) { + etest.flags |= ETH_TEST_FL_FAILED; + tests[3] = 1; + } + if (b57_test_intr(pUmDevice) == 0) { + etest.flags |= ETH_TEST_FL_FAILED; + tests[4] = 1; + } + if (b57_test_link(pUmDevice) == 0) { + etest.flags |= ETH_TEST_FL_FAILED; + tests[5] = 1; + } + if (old_power_level != LM_POWER_STATE_D0) { + LM_SetPowerState(pDevice, old_power_level); + } + if (copy_to_user(useraddr, &etest, sizeof(etest))) { + return -EFAULT; + } + if (copy_to_user(useraddr + sizeof(etest), tests, + sizeof(tests))) { + return -EFAULT; + } + return 0; + } +#endif +#ifdef ETHTOOL_GTSO + case ETHTOOL_GTSO: { + struct ethtool_value edata = { ETHTOOL_GTSO }; + +#ifdef BCM_TSO + edata.data = + (dev->features & NETIF_F_TSO) != 0; +#else + edata.data = 0; +#endif + if (copy_to_user(useraddr, &edata, sizeof(edata))) + return -EFAULT; + return 0; + } +#endif +#ifdef ETHTOOL_STSO + case ETHTOOL_STSO: { +#ifdef BCM_TSO + struct ethtool_value edata; + + if(!capable(CAP_NET_ADMIN)) + return -EPERM; + if (copy_from_user(&edata, useraddr, sizeof(edata))) + return -EFAULT; + if (!(pDevice->TaskToOffload & + LM_TASK_OFFLOAD_TCP_SEGMENTATION)) + { + return -EINVAL; + } + if (edata.data) { + dev->features |= NETIF_F_TSO; + } + else { + dev->features &= ~NETIF_F_TSO; + } + return 0; +#else + return -EINVAL; +#endif + } +#endif + } + + return -EOPNOTSUPP; +} +#endif /* #ifdef SIOCETHTOOL */ + +/* Provide ioctl() calls to examine the MII xcvr state. */ +STATIC int bcm5700_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) +{ + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK)dev->priv; + PLM_DEVICE_BLOCK pDevice = (PLM_DEVICE_BLOCK) pUmDevice; + u16 *data = (u16 *)&rq->ifr_data; + u32 value; + unsigned long flags; + + switch(cmd) { +#ifdef SIOCGMIIPHY + case SIOCGMIIPHY: +#endif + case SIOCDEVPRIVATE: /* Get the address of the PHY in use. */ + data[0] = pDevice->PhyAddr; + +#ifdef SIOCGMIIREG + case SIOCGMIIREG: +#endif + case SIOCDEVPRIVATE+1: /* Read the specified MII register. */ + if (pDevice->TbiFlags & ENABLE_TBI_FLAG) + return -EOPNOTSUPP; + + /* workaround for DHCP using ifup script */ + /* ifup only waits for 5 seconds for link up */ + /* NIC may take more than 5 seconds to establish link */ + if ((pUmDevice->delayed_link_ind > 0) && + delay_link[pUmDevice->index]) { + return -EOPNOTSUPP; + } + + BCM5700_PHY_LOCK(pUmDevice, flags); + LM_ReadPhy(pDevice, data[1] & 0x1f, (LM_UINT32 *) &value); + BCM5700_PHY_UNLOCK(pUmDevice, flags); + data[3] = value & 0xffff; + return 0; + +#ifdef SIOCSMIIREG + case SIOCSMIIREG: +#endif + case SIOCDEVPRIVATE+2: /* Write the specified MII register */ + if (!capable(CAP_NET_ADMIN)) + return -EPERM; + + if (pDevice->TbiFlags & ENABLE_TBI_FLAG) + return -EOPNOTSUPP; + + BCM5700_PHY_LOCK(pUmDevice, flags); + LM_WritePhy(pDevice, data[1] & 0x1f, data[2]); + BCM5700_PHY_UNLOCK(pUmDevice, flags); + return 0; + +#ifdef NICE_SUPPORT + case SIOCNICE: + { + struct nice_req* nrq; + + if (!capable(CAP_NET_ADMIN)) + return -EPERM; + + nrq = (struct nice_req*)&rq->ifr_ifru; + if( nrq->cmd == NICE_CMD_QUERY_SUPPORT ) { + nrq->nrq_magic = NICE_DEVICE_MAGIC; + nrq->nrq_support_rx = 1; + nrq->nrq_support_vlan = 1; + nrq->nrq_support_get_speed = 1; +#ifdef BCM_NAPI_RXPOLL + nrq->nrq_support_rx_napi = 1; +#endif + return 0; + } +#ifdef BCM_NAPI_RXPOLL + else if( nrq->cmd == NICE_CMD_SET_RX_NAPI ) +#else + else if( nrq->cmd == NICE_CMD_SET_RX ) +#endif + { + pUmDevice->nice_rx = nrq->nrq_rx; + pUmDevice->nice_ctx = nrq->nrq_ctx; + bcm5700_set_vlan_mode(pUmDevice); + return 0; + } +#ifdef BCM_NAPI_RXPOLL + else if( nrq->cmd == NICE_CMD_GET_RX_NAPI ) +#else + else if( nrq->cmd == NICE_CMD_GET_RX ) +#endif + { + nrq->nrq_rx = pUmDevice->nice_rx; + nrq->nrq_ctx = pUmDevice->nice_ctx; + return 0; + } + else if( nrq->cmd == NICE_CMD_GET_SPEED ) { + nrq->nrq_speed = pUmDevice->line_speed; + return 0; + } + else { + if (!pUmDevice->opened) + return -EINVAL; + + switch (nrq->cmd) { + case NICE_CMD_BLINK_LED: + if (LM_BlinkLED(pDevice, nrq->nrq_blink_time) == + LM_STATUS_SUCCESS) { + return 0; + } + return -EINTR; + + case NICE_CMD_DIAG_SUSPEND: + b57_suspend_chip(pUmDevice); + return 0; + + case NICE_CMD_DIAG_RESUME: + b57_resume_chip(pUmDevice); + return 0; + + case NICE_CMD_REG_READ: + if (nrq->nrq_offset >= 0x10000) { + nrq->nrq_data = LM_RegRdInd(pDevice, + nrq->nrq_offset); + } + else { + nrq->nrq_data = LM_RegRd(pDevice, + nrq->nrq_offset); + } + return 0; + + case NICE_CMD_REG_WRITE: + if (nrq->nrq_offset >= 0x10000) { + LM_RegWrInd(pDevice, nrq->nrq_offset, + nrq->nrq_data); + } + else { + LM_RegWr(pDevice, nrq->nrq_offset, + nrq->nrq_data, FALSE); + } + return 0; + + case NICE_CMD_REG_READ_DIRECT: + case NICE_CMD_REG_WRITE_DIRECT: + if ((nrq->nrq_offset >= 0x10000) || + (pDevice->Flags & UNDI_FIX_FLAG)) { + return -EINVAL; + } + + if (nrq->cmd == NICE_CMD_REG_READ_DIRECT) { + nrq->nrq_data = REG_RD_OFFSET(pDevice, + nrq->nrq_offset); + } + else { + REG_WR_OFFSET(pDevice, nrq->nrq_offset, + nrq->nrq_data); + } + return 0; + + case NICE_CMD_MEM_READ: + nrq->nrq_data = LM_MemRdInd(pDevice, + nrq->nrq_offset); + return 0; + + case NICE_CMD_MEM_WRITE: + LM_MemWrInd(pDevice, nrq->nrq_offset, + nrq->nrq_data); + return 0; + + case NICE_CMD_CFG_READ32: + pci_read_config_dword(pUmDevice->pdev, + nrq->nrq_offset, (u32 *)&nrq->nrq_data); + return 0; + + case NICE_CMD_CFG_READ16: + pci_read_config_word(pUmDevice->pdev, + nrq->nrq_offset, (u16 *)&nrq->nrq_data); + return 0; + + case NICE_CMD_CFG_READ8: + pci_read_config_byte(pUmDevice->pdev, + nrq->nrq_offset, (u8 *)&nrq->nrq_data); + return 0; + + case NICE_CMD_CFG_WRITE32: + pci_write_config_dword(pUmDevice->pdev, + nrq->nrq_offset, (u32)nrq->nrq_data); + return 0; + + case NICE_CMD_CFG_WRITE16: + pci_write_config_word(pUmDevice->pdev, + nrq->nrq_offset, (u16)nrq->nrq_data); + return 0; + + case NICE_CMD_CFG_WRITE8: + pci_write_config_byte(pUmDevice->pdev, + nrq->nrq_offset, (u8)nrq->nrq_data); + return 0; + + case NICE_CMD_RESET: + bcm5700_reset(dev); + return 0; + + case NICE_CMD_ENABLE_MAC_LOOPBACK: + if (pDevice->LoopBackMode != 0) { + return -EINVAL; + } + + BCM5700_PHY_LOCK(pUmDevice, flags); + LM_EnableMacLoopBack(pDevice); + BCM5700_PHY_UNLOCK(pUmDevice, flags); + return 0; + + case NICE_CMD_DISABLE_MAC_LOOPBACK: + if (pDevice->LoopBackMode != + LM_MAC_LOOP_BACK_MODE) { + return -EINVAL; + } + + BCM5700_PHY_LOCK(pUmDevice, flags); + LM_DisableMacLoopBack(pDevice); + BCM5700_PHY_UNLOCK(pUmDevice, flags); + return 0; + + case NICE_CMD_ENABLE_PHY_LOOPBACK: + if (pDevice->LoopBackMode != 0) { + return -EINVAL; + } + + BCM5700_PHY_LOCK(pUmDevice, flags); + LM_EnablePhyLoopBack(pDevice); + BCM5700_PHY_UNLOCK(pUmDevice, flags); + return 0; + + case NICE_CMD_DISABLE_PHY_LOOPBACK: + if (pDevice->LoopBackMode != + LM_PHY_LOOP_BACK_MODE) { + return -EINVAL; + } + + BCM5700_PHY_LOCK(pUmDevice, flags); + LM_DisablePhyLoopBack(pDevice); + BCM5700_PHY_UNLOCK(pUmDevice, flags); + return 0; + + case NICE_CMD_ENABLE_EXT_LOOPBACK: + if (pDevice->LoopBackMode != 0) { + return -EINVAL; + } + + if (pDevice->TbiFlags & ENABLE_TBI_FLAG) { + if (nrq->nrq_speed != 1000) + return -EINVAL; + } + else { + if ((nrq->nrq_speed != 1000) && + (nrq->nrq_speed != 100) && + (nrq->nrq_speed != 10)) { + return -EINVAL; + } + } + BCM5700_PHY_LOCK(pUmDevice, flags); + LM_EnableExtLoopBack(pDevice, nrq->nrq_speed); + BCM5700_PHY_UNLOCK(pUmDevice, flags); + return 0; + + case NICE_CMD_DISABLE_EXT_LOOPBACK: + if (pDevice->LoopBackMode != + LM_EXT_LOOP_BACK_MODE) { + return -EINVAL; + } + + BCM5700_PHY_LOCK(pUmDevice, flags); + LM_DisableExtLoopBack(pDevice); + BCM5700_PHY_UNLOCK(pUmDevice, flags); + return 0; + + case NICE_CMD_INTERRUPT_TEST: + nrq->nrq_intr_test_result = + b57_test_intr(pUmDevice); + return 0; + + case NICE_CMD_KMALLOC_PHYS: { +#if (LINUX_VERSION_CODE >= 0x020400) + dma_addr_t mapping; + __u64 cpu_pa; + void *ptr; + int i; + struct page *pg, *last_pg; + + for (i = 0; i < MAX_MEM2; i++) { + if (pUmDevice->mem_size_list2[i] == 0) + break; + } + if (i >= MAX_MEM2) + return -EFAULT; + ptr = pci_alloc_consistent(pUmDevice->pdev, + nrq->nrq_size, &mapping); + if (!ptr) { + return -EFAULT; + } + pUmDevice->mem_size_list2[i] = nrq->nrq_size; + pUmDevice->mem_list2[i] = ptr; + pUmDevice->dma_list2[i] = mapping; + + /* put pci mapping at the beginning of buffer */ + *((__u64 *) ptr) = (__u64) mapping; + + /* Probably won't work on some architectures */ + /* get CPU mapping */ + cpu_pa = (__u64) virt_to_phys(ptr); + pUmDevice->cpu_pa_list2[i] = cpu_pa; + nrq->nrq_phys_addr_lo = (__u32) cpu_pa; + nrq->nrq_phys_addr_hi = (__u32) (cpu_pa >> 32); + + pg = virt_to_page(ptr); + last_pg = virt_to_page(ptr + nrq->nrq_size - 1); + for (; ; pg++) { +#if (LINUX_VERSION_CODE > 0x020500) + SetPageReserved(pg); +#else + mem_map_reserve(pg); +#endif + if (pg == last_pg) + break; + } + return 0; +#else + return -EOPNOTSUPP; +#endif + } + case NICE_CMD_KFREE_PHYS: { + int i; + __u64 cpu_pa; + + cpu_pa = (__u64) nrq->nrq_phys_addr_lo + + ((__u64) nrq->nrq_phys_addr_hi << 32); + for (i = 0; i < MAX_MEM2; i++) { + if (pUmDevice->cpu_pa_list2[i] == + cpu_pa) + { + break; + } + } + if (i >= MAX_MEM2) + return -EFAULT; + + bcm5700_freemem2(pUmDevice, i); + return 0; + } + case NICE_CMD_SET_WRITE_PROTECT: + if (nrq->nrq_write_protect) + pDevice->Flags |= EEPROM_WP_FLAG; + else + pDevice->Flags &= ~EEPROM_WP_FLAG; + return 0; + case NICE_CMD_GET_STATS_BLOCK: { + PT3_STATS_BLOCK pStats = + (PT3_STATS_BLOCK)pDevice->pStatsBlkVirt; + if (copy_to_user(nrq->nrq_stats_useraddr, + pStats, nrq->nrq_stats_size)) { + return -EFAULT; + } + return 0; + } + case NICE_CMD_CLR_STATS_BLOCK: { + int j; + PT3_STATS_BLOCK pStats = + (PT3_STATS_BLOCK)pDevice->pStatsBlkVirt; + + memset(pStats, 0, sizeof(T3_STATS_BLOCK)); + if (T3_ASIC_REV(pDevice->ChipRevId) == + T3_ASIC_REV_5705) { + return 0; + } + for(j = 0x0300; j < 0x0b00; j = j + 4) { + MEM_WR_OFFSET(pDevice, j, 0); + } + + return 0; + } + } + } + return -EOPNOTSUPP; + } +#endif /* NICE_SUPPORT */ +#ifdef SIOCETHTOOL + case SIOCETHTOOL: + return netdev_ethtool_ioctl(dev, (void *) rq->ifr_data); +#endif + default: + return -EOPNOTSUPP; + } + return -EOPNOTSUPP; +} + +STATIC void bcm5700_set_rx_mode(struct net_device *dev) +{ + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK)dev->priv; + PLM_DEVICE_BLOCK pDevice = (PLM_DEVICE_BLOCK) pUmDevice; + int i; + struct dev_mc_list *mclist; + unsigned long flags; + + BCM5700_PHY_LOCK(pUmDevice, flags); + + LM_MulticastClear(pDevice); + for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count; + i++, mclist = mclist->next) { + LM_MulticastAdd(pDevice, (PLM_UINT8) &mclist->dmi_addr); + } + if (dev->flags & IFF_ALLMULTI) { + if (!(pDevice->ReceiveMask & LM_ACCEPT_ALL_MULTICAST)) { + LM_SetReceiveMask(pDevice, + pDevice->ReceiveMask | LM_ACCEPT_ALL_MULTICAST); + } + } + else if (pDevice->ReceiveMask & LM_ACCEPT_ALL_MULTICAST) { + LM_SetReceiveMask(pDevice, + pDevice->ReceiveMask & ~LM_ACCEPT_ALL_MULTICAST); + } + if (dev->flags & IFF_PROMISC) { + if (!(pDevice->ReceiveMask & LM_PROMISCUOUS_MODE)) { + LM_SetReceiveMask(pDevice, + pDevice->ReceiveMask | LM_PROMISCUOUS_MODE); + } + } + else if (pDevice->ReceiveMask & LM_PROMISCUOUS_MODE) { + LM_SetReceiveMask(pDevice, + pDevice->ReceiveMask & ~LM_PROMISCUOUS_MODE); + } + + BCM5700_PHY_UNLOCK(pUmDevice, flags); +} + +/* + * Set the hardware MAC address. + */ +STATIC int bcm5700_set_mac_addr(struct net_device *dev, void *p) +{ + struct sockaddr *addr=p; + PLM_DEVICE_BLOCK pDevice = (PLM_DEVICE_BLOCK) dev->priv; + UM_DEVICE_BLOCK *pUmDevice = (UM_DEVICE_BLOCK *) pDevice; + + memcpy(dev->dev_addr, addr->sa_data,dev->addr_len); + if (pUmDevice->opened) + LM_SetMacAddress(pDevice, dev->dev_addr); + return 0; +} + +#if T3_JUMBO_RCV_RCB_ENTRY_COUNT +STATIC int bcm5700_change_mtu(struct net_device *dev, int new_mtu) +{ + int pkt_size = new_mtu + ETHERNET_PACKET_HEADER_SIZE; + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK)dev->priv; + PLM_DEVICE_BLOCK pDevice = &pUmDevice->lm_dev; + unsigned long flags; + int reinit = 0; + + if ((pkt_size < MIN_ETHERNET_PACKET_SIZE_NO_CRC) || + (pkt_size > MAX_ETHERNET_JUMBO_PACKET_SIZE_NO_CRC)) { + + return -EINVAL; + } + if ((T3_ASIC_5705_OR_5750(pDevice->ChipRevId)) && + (pkt_size > MAX_ETHERNET_PACKET_SIZE_NO_CRC)) { + + return -EINVAL; + } + if (pUmDevice->suspended) + return -EAGAIN; + + if (pUmDevice->opened && (new_mtu != dev->mtu) && + !(T3_ASIC_5705_OR_5750(pDevice->ChipRevId))) { + reinit = 1; + } + + BCM5700_PHY_LOCK(pUmDevice, flags); + if (reinit) { + netif_stop_queue(dev); + bcm5700_shutdown(pUmDevice); + bcm5700_freemem(dev); + } + + dev->mtu = new_mtu; + if (pkt_size < MAX_ETHERNET_PACKET_SIZE_NO_CRC) { + pDevice->RxMtu = pDevice->TxMtu = + MAX_ETHERNET_PACKET_SIZE_NO_CRC; + } + else { + pDevice->RxMtu = pDevice->TxMtu = pkt_size; + } + + if (dev->mtu <= 1514) { + pDevice->RxJumboDescCnt = 0; + } + else { + pDevice->RxJumboDescCnt = + rx_jumbo_desc_cnt[pUmDevice->index]; + } + pDevice->RxPacketDescCnt = pDevice->RxJumboDescCnt + + pDevice->RxStdDescCnt; + + pDevice->RxJumboBufferSize = (pDevice->RxMtu + 8 /* CRC + VLAN */ + + COMMON_CACHE_LINE_SIZE-1) & ~COMMON_CACHE_LINE_MASK; + + if (reinit) { + LM_InitializeAdapter(pDevice); + bcm5700_set_vlan_mode(pUmDevice); + bcm5700_init_counters(pUmDevice); + if (memcmp(dev->dev_addr, pDevice->NodeAddress, 6)) { + LM_SetMacAddress(pDevice, dev->dev_addr); + } + netif_start_queue(dev); + bcm5700_intr_on(pUmDevice); + } + BCM5700_PHY_UNLOCK(pUmDevice, flags); + + return 0; +} +#endif + + +#if (LINUX_VERSION_CODE < 0x020300) + +int +bcm5700_probe(struct net_device *dev) +{ + int cards_found = 0; + struct pci_dev *pdev = NULL; + struct pci_device_id *pci_tbl; + u16 ssvid, ssid; + + if ( ! pci_present()) + return -ENODEV; + + pci_tbl = bcm5700_pci_tbl; + while ((pdev = pci_find_class(PCI_CLASS_NETWORK_ETHERNET << 8, pdev))) { + int idx; + + pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &ssvid); + pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &ssid); + for (idx = 0; pci_tbl[idx].vendor; idx++) { + if ((pci_tbl[idx].vendor == PCI_ANY_ID || + pci_tbl[idx].vendor == pdev->vendor) && + (pci_tbl[idx].device == PCI_ANY_ID || + pci_tbl[idx].device == pdev->device) && + (pci_tbl[idx].subvendor == PCI_ANY_ID || + pci_tbl[idx].subvendor == ssvid) && + (pci_tbl[idx].subdevice == PCI_ANY_ID || + pci_tbl[idx].subdevice == ssid)) + { + + break; + } + } + if (pci_tbl[idx].vendor == 0) + continue; + + + if (bcm5700_init_one(pdev, &pci_tbl[idx]) == 0) + cards_found++; + } + + return cards_found ? 0 : -ENODEV; +} + +#ifdef MODULE +int init_module(void) +{ + return bcm5700_probe(NULL); +} + +void cleanup_module(void) +{ + struct net_device *next_dev; + PUM_DEVICE_BLOCK pUmDevice; + + /* No need to check MOD_IN_USE, as sys_delete_module() checks. */ + while (root_tigon3_dev) { + pUmDevice = (PUM_DEVICE_BLOCK)root_tigon3_dev->priv; +#ifdef BCM_PROC_FS + bcm5700_proc_remove_dev(root_tigon3_dev); +#endif + next_dev = pUmDevice->next_module; + unregister_netdev(root_tigon3_dev); + if (pUmDevice->lm_dev.pMappedMemBase) + iounmap(pUmDevice->lm_dev.pMappedMemBase); +#if (LINUX_VERSION_CODE < 0x020600) + kfree(root_tigon3_dev); +#else + free_netdev(root_tigon3_dev); +#endif + root_tigon3_dev = next_dev; + } +#ifdef BCM_IOCTL32 + unregister_ioctl32_conversion(SIOCNICE); +#endif +} + +#endif /* MODULE */ +#else /* LINUX_VERSION_CODE < 0x020300 */ + +#if (LINUX_VERSION_CODE >= 0x020406) +static int bcm5700_suspend (struct pci_dev *pdev, u32 state) +#else +static void bcm5700_suspend (struct pci_dev *pdev) +#endif +{ + struct net_device *dev = (struct net_device *) pci_get_drvdata(pdev); + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) dev->priv; + PLM_DEVICE_BLOCK pDevice = &pUmDevice->lm_dev; + + if (!netif_running(dev)) +#if (LINUX_VERSION_CODE >= 0x020406) + return 0; +#else + return; +#endif + + netif_device_detach (dev); + bcm5700_shutdown(pUmDevice); + LM_SetPowerState(pDevice, LM_POWER_STATE_D3); + +/* pci_power_off(pdev, -1);*/ +#if (LINUX_VERSION_CODE >= 0x020406) + return 0; +#endif +} + + +#if (LINUX_VERSION_CODE >= 0x020406) +static int bcm5700_resume(struct pci_dev *pdev) +#else +static void bcm5700_resume(struct pci_dev *pdev) +#endif +{ + struct net_device *dev = (struct net_device *) pci_get_drvdata(pdev); + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) dev->priv; + PLM_DEVICE_BLOCK pDevice = &pUmDevice->lm_dev; + + if (!netif_running(dev)) +#if (LINUX_VERSION_CODE >= 0x020406) + return 0; +#else + return; +#endif +/* pci_power_on(pdev);*/ + netif_device_attach(dev); + LM_SetPowerState(pDevice, LM_POWER_STATE_D0); + MM_InitializeUmPackets(pDevice); + bcm5700_reset(dev); +#if (LINUX_VERSION_CODE >= 0x020406) + return 0; +#endif +} + + +static struct pci_driver bcm5700_pci_driver = { + name: bcm5700_driver, + id_table: bcm5700_pci_tbl, + probe: bcm5700_init_one, + remove: __devexit_p(bcm5700_remove_one), + suspend: bcm5700_suspend, + resume: bcm5700_resume, +}; + + +static int __init bcm5700_init_module (void) +{ + return pci_module_init(&bcm5700_pci_driver); +} + + +static void __exit bcm5700_cleanup_module (void) +{ + pci_unregister_driver(&bcm5700_pci_driver); +} + + +module_init(bcm5700_init_module); +module_exit(bcm5700_cleanup_module); +#endif + +/* + * Middle Module + * + */ + + +#ifdef BCM_NAPI_RXPOLL +LM_STATUS +MM_ScheduleRxPoll(LM_DEVICE_BLOCK *pDevice) +{ + struct net_device *dev = ((UM_DEVICE_BLOCK *) pDevice)->dev; + + if (netif_rx_schedule_prep(dev)) { + __netif_rx_schedule(dev); + return LM_STATUS_SUCCESS; + } + return LM_STATUS_FAILURE; +} +#endif + +LM_STATUS +MM_ReadConfig16(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset, + LM_UINT16 *pValue16) +{ + UM_DEVICE_BLOCK *pUmDevice; + + pUmDevice = (UM_DEVICE_BLOCK *) pDevice; + pci_read_config_word(pUmDevice->pdev, Offset, (u16 *) pValue16); + return LM_STATUS_SUCCESS; +} + +LM_STATUS +MM_ReadConfig32(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset, + LM_UINT32 *pValue32) +{ + UM_DEVICE_BLOCK *pUmDevice; + + pUmDevice = (UM_DEVICE_BLOCK *) pDevice; + pci_read_config_dword(pUmDevice->pdev, Offset, (u32 *) pValue32); + return LM_STATUS_SUCCESS; +} + +LM_STATUS +MM_WriteConfig16(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset, + LM_UINT16 Value16) +{ + UM_DEVICE_BLOCK *pUmDevice; + + pUmDevice = (UM_DEVICE_BLOCK *) pDevice; + pci_write_config_word(pUmDevice->pdev, Offset, Value16); + return LM_STATUS_SUCCESS; +} + +LM_STATUS +MM_WriteConfig32(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset, + LM_UINT32 Value32) +{ + UM_DEVICE_BLOCK *pUmDevice; + + pUmDevice = (UM_DEVICE_BLOCK *) pDevice; + pci_write_config_dword(pUmDevice->pdev, Offset, Value32); + return LM_STATUS_SUCCESS; +} + +LM_STATUS +MM_AllocateSharedMemory(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlockSize, + PLM_VOID *pMemoryBlockVirt, PLM_PHYSICAL_ADDRESS pMemoryBlockPhy, + LM_BOOL Cached) +{ + PLM_VOID pvirt; + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; + dma_addr_t mapping; + + pvirt = pci_alloc_consistent(pUmDevice->pdev, BlockSize, + &mapping); + if (!pvirt) { + return LM_STATUS_FAILURE; + } + pUmDevice->mem_list[pUmDevice->mem_list_num] = pvirt; + pUmDevice->dma_list[pUmDevice->mem_list_num] = mapping; + pUmDevice->mem_size_list[pUmDevice->mem_list_num++] = BlockSize; + memset(pvirt, 0, BlockSize); + *pMemoryBlockVirt = (PLM_VOID) pvirt; + MM_SetAddr(pMemoryBlockPhy, mapping); + return LM_STATUS_SUCCESS; +} + +LM_STATUS +MM_AllocateMemory(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlockSize, + PLM_VOID *pMemoryBlockVirt) +{ + PLM_VOID pvirt; + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; + + + /* Maximum in slab.c */ + if (BlockSize > 131072) { + goto MM_Alloc_error; + } + + pvirt = kmalloc(BlockSize, GFP_KERNEL); + if (!pvirt) { + goto MM_Alloc_error; + } + pUmDevice->mem_list[pUmDevice->mem_list_num] = pvirt; + pUmDevice->dma_list[pUmDevice->mem_list_num] = 0; + pUmDevice->mem_size_list[pUmDevice->mem_list_num++] = 0; + /* mem_size_list[i] == 0 indicates that the memory should be freed */ + /* using kfree */ + memset(pvirt, 0, BlockSize); + *pMemoryBlockVirt = pvirt; + return LM_STATUS_SUCCESS; + +MM_Alloc_error: + printk(KERN_WARNING "%s: Memory allocation failed - buffer parameters may be set too high\n", pUmDevice->dev->name); + return LM_STATUS_FAILURE; +} + +LM_STATUS +MM_MapMemBase(PLM_DEVICE_BLOCK pDevice) +{ + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; + + pDevice->pMappedMemBase = ioremap_nocache( + pci_resource_start(pUmDevice->pdev, 0), sizeof(T3_STD_MEM_MAP)); + if (pDevice->pMappedMemBase == 0) + return LM_STATUS_FAILURE; + + return LM_STATUS_SUCCESS; +} + +LM_STATUS +MM_InitializeUmPackets(PLM_DEVICE_BLOCK pDevice) +{ + unsigned int i; + struct sk_buff *skb; + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; + PUM_PACKET pUmPacket; + PLM_PACKET pPacket; + + for (i = 0; i < pDevice->RxPacketDescCnt; i++) { + pPacket = QQ_PopHead(&pDevice->RxPacketFreeQ.Container); + pUmPacket = (PUM_PACKET) pPacket; + if (pPacket == 0) { + printk(KERN_DEBUG "Bad RxPacketFreeQ\n"); + } + if (pUmPacket->skbuff == 0) { + skb = dev_alloc_skb(pPacket->u.Rx.RxBufferSize + 2); + if (skb == 0) { + pUmPacket->skbuff = 0; + QQ_PushTail( + &pUmDevice->rx_out_of_buf_q.Container, + pPacket); + continue; + } + pUmPacket->skbuff = skb; + skb->dev = pUmDevice->dev; + skb_reserve(skb, pUmDevice->rx_buf_align); + } + QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket); + } + if (T3_ASIC_REV(pUmDevice->lm_dev.ChipRevId) == T3_ASIC_REV_5700) { + /* reallocate buffers in the ISR */ + pUmDevice->rx_buf_repl_thresh = 0; + pUmDevice->rx_buf_repl_panic_thresh = 0; + pUmDevice->rx_buf_repl_isr_limit = 0; + } + else { + pUmDevice->rx_buf_repl_thresh = pDevice->RxPacketDescCnt / 8; + pUmDevice->rx_buf_repl_panic_thresh = + pDevice->RxPacketDescCnt * 7 / 8; + + /* This limits the time spent in the ISR when the receiver */ + /* is in a steady state of being overrun. */ + pUmDevice->rx_buf_repl_isr_limit = pDevice->RxPacketDescCnt / 8; + +#if T3_JUMBO_RCV_RCB_ENTRY_COUNT + if (pDevice->RxJumboDescCnt != 0) { + if (pUmDevice->rx_buf_repl_thresh >= + pDevice->RxJumboDescCnt) { + + pUmDevice->rx_buf_repl_thresh = + pUmDevice->rx_buf_repl_panic_thresh = + pDevice->RxJumboDescCnt - 1; + } + if (pUmDevice->rx_buf_repl_thresh >= + pDevice->RxStdDescCnt) { + + pUmDevice->rx_buf_repl_thresh = + pUmDevice->rx_buf_repl_panic_thresh = + pDevice->RxStdDescCnt - 1; + } + } +#endif + } + return LM_STATUS_SUCCESS; +} + +LM_STATUS +MM_GetConfig(PLM_DEVICE_BLOCK pDevice) +{ + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; + int index = pUmDevice->index; + struct net_device *dev = pUmDevice->dev; + + bcm5700_validate_param_range(pUmDevice, &auto_speed[index], "auto_speed", + 0, 1, 1); + if (auto_speed[index] == 0) + pDevice->DisableAutoNeg = TRUE; + else + pDevice->DisableAutoNeg = FALSE; + + if (line_speed[index] == 0) { + pDevice->RequestedLineSpeed = LM_LINE_SPEED_AUTO; + pDevice->DisableAutoNeg = FALSE; + } + else { + bcm5700_validate_param_range(pUmDevice, &full_duplex[index], + "full_duplex", 0, 1, 1); + if (full_duplex[index]) { + pDevice->RequestedDuplexMode = LM_DUPLEX_MODE_FULL; + } + else { + pDevice->RequestedDuplexMode = LM_DUPLEX_MODE_HALF; + } + + if (line_speed[index] == 1000) { + pDevice->RequestedLineSpeed = LM_LINE_SPEED_1000MBPS; + if (pDevice->PhyFlags & PHY_NO_GIGABIT) { + pDevice->RequestedLineSpeed = + LM_LINE_SPEED_100MBPS; + printk(KERN_WARNING "%s-%d: Invalid line_speed parameter (1000), using 100\n", bcm5700_driver, index); + } + else { + if ((pDevice->TbiFlags & ENABLE_TBI_FLAG) && + !full_duplex[index]) { + + printk(KERN_WARNING "%s-%d: Invalid full_duplex parameter (0) for fiber, using 1\n", bcm5700_driver, index); + pDevice->RequestedDuplexMode = + LM_DUPLEX_MODE_FULL; + } + + if ((pDevice->TbiFlags & ENABLE_TBI_FLAG) && + !auto_speed[index]) { + printk(KERN_WARNING "%s-%d: Invalid auto_speed parameter (0) for copper, using 1\n", bcm5700_driver, index); + pDevice->DisableAutoNeg = FALSE; + } + } + } + else if (line_speed[index] == 100) { + pDevice->RequestedLineSpeed = LM_LINE_SPEED_100MBPS; + } + else if (line_speed[index] == 10) { + pDevice->RequestedLineSpeed = LM_LINE_SPEED_10MBPS; + } + else { + pDevice->RequestedLineSpeed = LM_LINE_SPEED_AUTO; + pDevice->DisableAutoNeg = FALSE; + printk(KERN_WARNING "%s-%d: Invalid line_speed parameter (%d), using 0\n", bcm5700_driver, index, line_speed[index]); + } + + } + pDevice->FlowControlCap = 0; + bcm5700_validate_param_range(pUmDevice, &rx_flow_control[index], + "rx_flow_control", 0, 1, 0); + if (rx_flow_control[index] != 0) { + pDevice->FlowControlCap |= LM_FLOW_CONTROL_RECEIVE_PAUSE; + } + bcm5700_validate_param_range(pUmDevice, &tx_flow_control[index], + "tx_flow_control", 0, 1, 0); + if (tx_flow_control[index] != 0) { + pDevice->FlowControlCap |= LM_FLOW_CONTROL_TRANSMIT_PAUSE; + } + bcm5700_validate_param_range(pUmDevice, &auto_flow_control[index], + "auto_flow_control", 0, 1, 0); + if (auto_flow_control[index] != 0) { + if (pDevice->DisableAutoNeg == FALSE) { + + pDevice->FlowControlCap |= LM_FLOW_CONTROL_AUTO_PAUSE; + if ((tx_flow_control[index] == 0) && + (rx_flow_control[index] == 0)) { + + pDevice->FlowControlCap |= + LM_FLOW_CONTROL_TRANSMIT_PAUSE | + LM_FLOW_CONTROL_RECEIVE_PAUSE; + } + } + } + + if (dev->mtu > 1500) { + pDevice->RxMtu = dev->mtu + 14; + } + + if ((T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700) && + !(pDevice->Flags & BCM5788_FLAG)) { + pDevice->Flags |= USE_TAGGED_STATUS_FLAG; + pUmDevice->timer_interval = HZ; + if ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703) && + (pDevice->TbiFlags & ENABLE_TBI_FLAG)) { + pUmDevice->timer_interval = HZ/4; + } + } + else { + pUmDevice->timer_interval = HZ/10; + } + + bcm5700_validate_param_range(pUmDevice, &tx_pkt_desc_cnt[index], + "tx_pkt_desc_cnt", 1, MAX_TX_PACKET_DESC_COUNT-1, TX_DESC_CNT); + pDevice->TxPacketDescCnt = tx_pkt_desc_cnt[index]; + bcm5700_validate_param_range(pUmDevice, &rx_std_desc_cnt[index], + "rx_std_desc_cnt", 1, T3_STD_RCV_RCB_ENTRY_COUNT-1, + RX_DESC_CNT); + pDevice->RxStdDescCnt = rx_std_desc_cnt[index]; + +#if T3_JUMBO_RCV_RCB_ENTRY_COUNT + bcm5700_validate_param_range(pUmDevice, &rx_jumbo_desc_cnt[index], + "rx_jumbo_desc_cnt", 1, T3_JUMBO_RCV_RCB_ENTRY_COUNT-1, + JBO_DESC_CNT); + + if (mtu[index] <= 1514) + pDevice->RxJumboDescCnt = 0; + else + pDevice->RxJumboDescCnt = rx_jumbo_desc_cnt[index]; +#endif + +#ifdef BCM_INT_COAL + bcm5700_validate_param_range(pUmDevice, &adaptive_coalesce[index], + "adaptive_coalesce", 0, 1, 1); +#ifdef BCM_NAPI_RXPOLL + if (adaptive_coalesce[index]) { + printk(KERN_WARNING "%s-%d: adaptive_coalesce not used in NAPI mode\n", bcm5700_driver, index); + adaptive_coalesce[index] = 0; + + } +#endif + pUmDevice->adaptive_coalesce = adaptive_coalesce[index]; + if (!pUmDevice->adaptive_coalesce) { + bcm5700_validate_param_range(pUmDevice, + &rx_coalesce_ticks[index], "rx_coalesce_ticks", 0, + MAX_RX_COALESCING_TICKS, RX_COAL_TK); + if ((rx_coalesce_ticks[index] == 0) && + (rx_max_coalesce_frames[index] == 0)) { + + printk(KERN_WARNING "%s-%d: Conflicting rx_coalesce_ticks (0) and rx_max_coalesce_frames (0) parameters, using %d and %d respectively\n", + bcm5700_driver, index, RX_COAL_TK, RX_COAL_FM); + + rx_coalesce_ticks[index] = RX_COAL_TK; + rx_max_coalesce_frames[index] = RX_COAL_FM; + } + pDevice->RxCoalescingTicks = pUmDevice->rx_curr_coalesce_ticks = + rx_coalesce_ticks[index]; +#ifdef BCM_NAPI_RXPOLL + pDevice->RxCoalescingTicksDuringInt = rx_coalesce_ticks[index]; +#endif + + bcm5700_validate_param_range(pUmDevice, + &rx_max_coalesce_frames[index], + "rx_max_coalesce_frames", 0, + MAX_RX_MAX_COALESCED_FRAMES, RX_COAL_FM); + + pDevice->RxMaxCoalescedFrames = + pUmDevice->rx_curr_coalesce_frames = + rx_max_coalesce_frames[index]; +#ifdef BCM_NAPI_RXPOLL + pDevice->RxMaxCoalescedFramesDuringInt = + rx_max_coalesce_frames[index]; +#endif + + bcm5700_validate_param_range(pUmDevice, + &tx_coalesce_ticks[index], "tx_coalesce_ticks", 0, + MAX_TX_COALESCING_TICKS, TX_COAL_TK); + if ((tx_coalesce_ticks[index] == 0) && + (tx_max_coalesce_frames[index] == 0)) { + + printk(KERN_WARNING "%s-%d: Conflicting tx_coalesce_ticks (0) and tx_max_coalesce_frames (0) parameters, using %d and %d respectively\n", + bcm5700_driver, index, TX_COAL_TK, TX_COAL_FM); + + tx_coalesce_ticks[index] = TX_COAL_TK; + tx_max_coalesce_frames[index] = TX_COAL_FM; + } + pDevice->TxCoalescingTicks = tx_coalesce_ticks[index]; + bcm5700_validate_param_range(pUmDevice, + &tx_max_coalesce_frames[index], + "tx_max_coalesce_frames", 0, + MAX_TX_MAX_COALESCED_FRAMES, TX_COAL_FM); + pDevice->TxMaxCoalescedFrames = tx_max_coalesce_frames[index]; + pUmDevice->tx_curr_coalesce_frames = + pDevice->TxMaxCoalescedFrames; + + bcm5700_validate_param_range(pUmDevice, + &stats_coalesce_ticks[index], "stats_coalesce_ticks", + 0, MAX_STATS_COALESCING_TICKS, ST_COAL_TK); + if ((stats_coalesce_ticks[index] > 0) && + (stats_coalesce_ticks[index] < 100)) { + printk(KERN_WARNING "%s-%d: Invalid stats_coalesce_ticks parameter (%u), using 100\n", bcm5700_driver, index, (unsigned int) stats_coalesce_ticks[index]); + stats_coalesce_ticks[index] = 100; + } + pDevice->StatsCoalescingTicks = stats_coalesce_ticks[index]; + pDevice->StatsCoalescingTicks = stats_coalesce_ticks[index]; + } + else { + pUmDevice->rx_curr_coalesce_frames = RX_COAL_FM; + pUmDevice->rx_curr_coalesce_ticks = RX_COAL_TK; + pUmDevice->tx_curr_coalesce_frames = TX_COAL_FM; + } +#endif + +#ifdef BCM_WOL + bcm5700_validate_param_range(pUmDevice, &enable_wol[index], + "enable_wol", 0, 1, 0); + if (enable_wol[index]) { + pDevice->WakeUpModeCap = LM_WAKE_UP_MODE_MAGIC_PACKET; + pDevice->WakeUpMode = LM_WAKE_UP_MODE_MAGIC_PACKET; + } +#endif +#ifdef BCM_NIC_SEND_BD + bcm5700_validate_param_range(pUmDevice, &nic_tx_bd[index], "nic_tx_bd", + 0, 1, 0); + if (nic_tx_bd[index]) + pDevice->Flags |= NIC_SEND_BD_FLAG; + if ((pDevice->Flags & ENABLE_PCIX_FIX_FLAG) || + (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5705)) { + if (pDevice->Flags & NIC_SEND_BD_FLAG) { + pDevice->Flags &= ~NIC_SEND_BD_FLAG; + printk(KERN_WARNING "%s-%d: Nic Send BDs not available on this NIC or not possible on this system\n", bcm5700_driver, index); + } + } +#endif +#if INCLUDE_TBI_SUPPORT + if (pDevice->TbiFlags & ENABLE_TBI_FLAG) { + if ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704) || + (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703)) { + /* just poll since we have hardware autoneg. in 5704 */ + pDevice->TbiFlags |= TBI_PURE_POLLING_FLAG; + } + else { + pDevice->TbiFlags |= TBI_POLLING_INTR_FLAG; + } + } +#endif + bcm5700_validate_param_range(pUmDevice, &scatter_gather[index], + "scatter_gather", 0, 1, 1); + bcm5700_validate_param_range(pUmDevice, &tx_checksum[index], + "tx_checksum", 0, 1, 1); + bcm5700_validate_param_range(pUmDevice, &rx_checksum[index], + "rx_checksum", 0, 1, 1); + if (!(pDevice->TaskOffloadCap & LM_TASK_OFFLOAD_TX_TCP_CHECKSUM)) { + if (tx_checksum[index] || rx_checksum[index]) { + + pDevice->TaskToOffload = LM_TASK_OFFLOAD_NONE; + printk(KERN_WARNING "%s-%d: Checksum offload not available on this NIC\n", bcm5700_driver, index); + } + } + else { + if (rx_checksum[index]) { + pDevice->TaskToOffload |= + LM_TASK_OFFLOAD_RX_TCP_CHECKSUM | + LM_TASK_OFFLOAD_RX_UDP_CHECKSUM; + } + if (tx_checksum[index]) { + pDevice->TaskToOffload |= + LM_TASK_OFFLOAD_TX_TCP_CHECKSUM | + LM_TASK_OFFLOAD_TX_UDP_CHECKSUM; + pDevice->Flags |= NO_TX_PSEUDO_HDR_CSUM_FLAG; + } + } +#ifdef BCM_TSO + bcm5700_validate_param_range(pUmDevice, &enable_tso[index], + "enable_tso", 0, 1, 1); + + /* Always enable TSO firmware if supported */ + /* This way we can turn it on or off on the fly */ + if (pDevice->TaskOffloadCap & LM_TASK_OFFLOAD_TCP_SEGMENTATION) + { + pDevice->TaskToOffload |= + LM_TASK_OFFLOAD_TCP_SEGMENTATION; + } + if (enable_tso[index] && + !(pDevice->TaskToOffload & LM_TASK_OFFLOAD_TCP_SEGMENTATION)) + { + printk(KERN_WARNING "%s-%d: TSO not available on this NIC\n", bcm5700_driver, index); + } +#endif +#ifdef BCM_ASF + bcm5700_validate_param_range(pUmDevice, &vlan_tag_mode[index], + "vlan_strip_mode", 0, 2, 0); + pUmDevice->vlan_tag_mode = vlan_tag_mode[index]; +#else + pUmDevice->vlan_tag_mode = VLAN_TAG_MODE_NORMAL_STRIP; +#endif + bcm5700_validate_param_range(pUmDevice, &delay_link[index], + "delay_link", 0, 1, 0); + bcm5700_validate_param_range(pUmDevice, &disable_d3hot[index], + "disable_d3hot", 0, 1, 0); + if (disable_d3hot[index]) { +#ifdef BCM_WOL + if (enable_wol[index]) { + pDevice->WakeUpModeCap = LM_WAKE_UP_MODE_NONE; + pDevice->WakeUpMode = LM_WAKE_UP_MODE_NONE; + printk(KERN_WARNING "%s-%d: Wake-On-Lan disabled because D3Hot is disabled\n", bcm5700_driver, index); + } +#endif + pDevice->Flags |= DISABLE_D3HOT_FLAG; + } + return LM_STATUS_SUCCESS; +} + +LM_STATUS +MM_IndicateRxPackets(PLM_DEVICE_BLOCK pDevice) +{ + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; + PLM_PACKET pPacket; + PUM_PACKET pUmPacket; + struct sk_buff *skb; + int size; + int vlan_tag_size = 0; + + if (pDevice->ReceiveMask & LM_KEEP_VLAN_TAG) + vlan_tag_size = 4; + + while (1) { + pPacket = (PLM_PACKET) + QQ_PopHead(&pDevice->RxPacketReceivedQ.Container); + if (pPacket == 0) + break; + pUmPacket = (PUM_PACKET) pPacket; +#if ! defined(NO_PCI_UNMAP) + pci_unmap_single(pUmDevice->pdev, + pci_unmap_addr(pUmPacket, map[0]), + pPacket->u.Rx.RxBufferSize, + PCI_DMA_FROMDEVICE); +#endif + if ((pPacket->PacketStatus != LM_STATUS_SUCCESS) || + ((size = pPacket->PacketSize) > + (pDevice->RxMtu + vlan_tag_size))) { + + /* reuse skb */ +#ifdef BCM_TASKLET + QQ_PushTail(&pUmDevice->rx_out_of_buf_q.Container, pPacket); +#else + QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket); +#endif + pUmDevice->rx_misc_errors++; + continue; + } + skb = pUmPacket->skbuff; + skb_put(skb, size); + skb->pkt_type = 0; + skb->protocol = eth_type_trans(skb, skb->dev); + if (size > pDevice->RxMtu) { + /* Make sure we have a valid VLAN tag */ + if (htons(skb->protocol) != 0x8100) { + dev_kfree_skb_irq(skb); + pUmDevice->rx_misc_errors++; + goto drop_rx; + } + } + if ((pPacket->Flags & RCV_BD_FLAG_TCP_UDP_CHKSUM_FIELD) && + (pDevice->TaskToOffload & + LM_TASK_OFFLOAD_RX_TCP_CHECKSUM)) { + if (pPacket->u.Rx.TcpUdpChecksum == 0xffff) { + + skb->ip_summed = CHECKSUM_UNNECESSARY; +#if TIGON3_DEBUG + pUmDevice->rx_good_chksum_count++; +#endif + } + else { + skb->ip_summed = CHECKSUM_NONE; + pUmDevice->rx_bad_chksum_count++; + } + } + else { + skb->ip_summed = CHECKSUM_NONE; + } +#ifdef NICE_SUPPORT + if( pUmDevice->nice_rx ) { + vlan_tag_t *vlan_tag; + + vlan_tag = (vlan_tag_t *) &skb->cb[0]; + if (pPacket->Flags & RCV_BD_FLAG_VLAN_TAG) { + vlan_tag->signature = 0x7777; + vlan_tag->tag = pPacket->VlanTag; + } + else { + vlan_tag->signature = 0; + } + pUmDevice->nice_rx(skb, pUmDevice->nice_ctx); + } + else +#endif + { +#ifdef BCM_VLAN + if (pUmDevice->vlgrp && + (pPacket->Flags & RCV_BD_FLAG_VLAN_TAG)) { + +#ifdef BCM_NAPI_RXPOLL + vlan_hwaccel_receive_skb(skb, pUmDevice->vlgrp, + pPacket->VlanTag); +#else + vlan_hwaccel_rx(skb, pUmDevice->vlgrp, + pPacket->VlanTag); +#endif + } + else +#endif + { +#ifdef BCM_NAPI_RXPOLL + netif_receive_skb(skb); +#else + netif_rx(skb); +#endif + } + } + pUmDevice->dev->last_rx = jiffies; + +drop_rx: +#ifdef BCM_TASKLET + pUmPacket->skbuff = 0; + QQ_PushTail(&pUmDevice->rx_out_of_buf_q.Container, pPacket); +#else + skb = dev_alloc_skb(pPacket->u.Rx.RxBufferSize + 2); + if (skb == 0) { + pUmPacket->skbuff = 0; + QQ_PushTail(&pUmDevice->rx_out_of_buf_q.Container, pPacket); + } + else { + pUmPacket->skbuff = skb; + skb->dev = pUmDevice->dev; + skb_reserve(skb, pUmDevice->rx_buf_align); + QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket); + } +#endif + } + return LM_STATUS_SUCCESS; +} + +LM_STATUS +MM_CoalesceTxBuffer(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket) +{ + PUM_PACKET pUmPacket = (PUM_PACKET) pPacket; + struct sk_buff *skb = pUmPacket->skbuff; + struct sk_buff *nskb; +#if ! defined(NO_PCI_UNMAP) + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; + + pci_unmap_single(pUmDevice->pdev, + pci_unmap_addr(pUmPacket, map[0]), + pci_unmap_len(pUmPacket, map_len[0]), + PCI_DMA_TODEVICE); +#if MAX_SKB_FRAGS + { + int i; + + for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { + pci_unmap_page(pUmDevice->pdev, + pci_unmap_addr(pUmPacket, map[i + 1]), + pci_unmap_len(pUmPacket, map_len[i + 1]), + PCI_DMA_TODEVICE); + } + } +#endif +#endif + if ((nskb = skb_copy(skb, GFP_ATOMIC))) { + pUmPacket->lm_packet.u.Tx.FragCount = 1; + dev_kfree_skb(skb); + pUmPacket->skbuff = nskb; + return LM_STATUS_SUCCESS; + } + dev_kfree_skb(skb); + pUmPacket->skbuff = 0; + return LM_STATUS_FAILURE; +} + +/* Returns 1 if not all buffers are allocated */ +STATIC int +replenish_rx_buffers(PUM_DEVICE_BLOCK pUmDevice, int max) +{ + PLM_PACKET pPacket; + PUM_PACKET pUmPacket; + PLM_DEVICE_BLOCK pDevice = (PLM_DEVICE_BLOCK) pUmDevice; + struct sk_buff *skb; + int queue_rx = 0; + int alloc_cnt = 0; + int ret = 0; + + while ((pUmPacket = (PUM_PACKET) + QQ_PopHead(&pUmDevice->rx_out_of_buf_q.Container)) != 0) { + pPacket = (PLM_PACKET) pUmPacket; + if (pUmPacket->skbuff) { + /* reuse an old skb */ + QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket); + queue_rx = 1; + continue; + } + if ((skb = dev_alloc_skb(pPacket->u.Rx.RxBufferSize + 2)) == 0) { + QQ_PushHead(&pUmDevice->rx_out_of_buf_q.Container, + pPacket); + ret = 1; + break; + } + pUmPacket->skbuff = skb; + skb->dev = pUmDevice->dev; + skb_reserve(skb, pUmDevice->rx_buf_align); + QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket); + queue_rx = 1; + if (max > 0) { + alloc_cnt++; + if (alloc_cnt >= max) + break; + } + } + if (queue_rx || pDevice->QueueAgain) { + LM_QueueRxPackets(pDevice); + } + return ret; +} + +LM_STATUS +MM_IndicateTxPackets(PLM_DEVICE_BLOCK pDevice) +{ + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; + PLM_PACKET pPacket; + PUM_PACKET pUmPacket; + struct sk_buff *skb; +#if ! defined(NO_PCI_UNMAP) && MAX_SKB_FRAGS + int i; +#endif + + while (1) { + pPacket = (PLM_PACKET) + QQ_PopHead(&pDevice->TxPacketXmittedQ.Container); + if (pPacket == 0) + break; + pUmPacket = (PUM_PACKET) pPacket; + skb = pUmPacket->skbuff; +#if ! defined(NO_PCI_UNMAP) + pci_unmap_single(pUmDevice->pdev, + pci_unmap_addr(pUmPacket, map[0]), + pci_unmap_len(pUmPacket, map_len[0]), + PCI_DMA_TODEVICE); +#if MAX_SKB_FRAGS + for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { + pci_unmap_page(pUmDevice->pdev, + pci_unmap_addr(pUmPacket, map[i + 1]), + pci_unmap_len(pUmPacket, map_len[i + 1]), + PCI_DMA_TODEVICE); + } +#endif +#endif + dev_kfree_skb_irq(skb); + pUmPacket->skbuff = 0; + QQ_PushTail(&pDevice->TxPacketFreeQ.Container, pPacket); + } + if (pUmDevice->tx_full) { + if (QQ_GetEntryCnt(&pDevice->TxPacketFreeQ.Container) >= + (pDevice->TxPacketDescCnt >> 1)) { + + pUmDevice->tx_full = 0; + netif_wake_queue(pUmDevice->dev); + } + } + return LM_STATUS_SUCCESS; +} + +LM_STATUS +MM_IndicateStatus(PLM_DEVICE_BLOCK pDevice, LM_STATUS Status) +{ + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; + struct net_device *dev = pUmDevice->dev; + LM_FLOW_CONTROL flow_control; + + if (!pUmDevice->opened) + return LM_STATUS_SUCCESS; + + if (pUmDevice->delayed_link_ind > 0) { + pUmDevice->delayed_link_ind = 0; + if (Status == LM_STATUS_LINK_DOWN) { + pUmDevice->line_speed = 0; + netif_carrier_off(dev); + printk(KERN_ERR "%s: %s NIC Link is DOWN\n", bcm5700_driver, dev->name); + } + else if (Status == LM_STATUS_LINK_ACTIVE) { + netif_carrier_on(dev); + printk(KERN_INFO "%s: %s NIC Link is UP, ", bcm5700_driver, dev->name); + } + } + else { + if (Status == LM_STATUS_LINK_DOWN) { + pUmDevice->line_speed = 0; + netif_carrier_off(dev); + printk(KERN_ERR "%s: %s NIC Link is Down\n", bcm5700_driver, dev->name); + } + else if (Status == LM_STATUS_LINK_ACTIVE) { + netif_carrier_on(dev); + printk(KERN_INFO "%s: %s NIC Link is Up, ", bcm5700_driver, dev->name); + } + } + + if (Status == LM_STATUS_LINK_ACTIVE) { + if (pDevice->LineSpeed == LM_LINE_SPEED_1000MBPS) + pUmDevice->line_speed = 1000; + else if (pDevice->LineSpeed == LM_LINE_SPEED_100MBPS) + pUmDevice->line_speed = 100; + else if (pDevice->LineSpeed == LM_LINE_SPEED_10MBPS) + pUmDevice->line_speed = 10; + + printk("%d Mbps ", pUmDevice->line_speed); + + if (pDevice->DuplexMode == LM_DUPLEX_MODE_FULL) + printk("full duplex"); + else + printk("half duplex"); + + flow_control = pDevice->FlowControl & + (LM_FLOW_CONTROL_RECEIVE_PAUSE | + LM_FLOW_CONTROL_TRANSMIT_PAUSE); + if (flow_control) { + if (flow_control & LM_FLOW_CONTROL_RECEIVE_PAUSE) { + printk(", receive "); + if (flow_control & LM_FLOW_CONTROL_TRANSMIT_PAUSE) + printk("& transmit "); + } + else { + printk(", transmit "); + } + printk("flow control ON"); + } + printk("\n"); + } + return LM_STATUS_SUCCESS; +} + +void +MM_UnmapRxDma(LM_DEVICE_BLOCK *pDevice, LM_PACKET *pPacket) +{ +#if ! defined(NO_PCI_UNMAP) + UM_DEVICE_BLOCK *pUmDevice = (UM_DEVICE_BLOCK *) pDevice; + UM_PACKET *pUmPacket = (UM_PACKET *) pPacket; + + if (!pUmPacket->skbuff) + return; + + pci_unmap_single(pUmDevice->pdev, + pci_unmap_addr(pUmPacket, map[0]), + pPacket->u.Rx.RxBufferSize, + PCI_DMA_FROMDEVICE); +#endif +} + +LM_STATUS +MM_FreeRxBuffer(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket) +{ + PUM_PACKET pUmPacket; + struct sk_buff *skb; + + if (pPacket == 0) + return LM_STATUS_SUCCESS; + pUmPacket = (PUM_PACKET) pPacket; + if ((skb = pUmPacket->skbuff)) { + /* DMA address already unmapped */ + dev_kfree_skb(skb); + } + pUmPacket->skbuff = 0; + return LM_STATUS_SUCCESS; +} + +LM_STATUS +MM_Sleep(LM_DEVICE_BLOCK *pDevice, LM_UINT32 msec) +{ + current->state = TASK_INTERRUPTIBLE; + if (schedule_timeout(HZ * msec / 1000) != 0) { + return LM_STATUS_FAILURE; + } + if (signal_pending(current)) + return LM_STATUS_FAILURE; + + return LM_STATUS_SUCCESS; +} + +void +bcm5700_shutdown(UM_DEVICE_BLOCK *pUmDevice) +{ + LM_DEVICE_BLOCK *pDevice = (LM_DEVICE_BLOCK *) pUmDevice; + + bcm5700_intr_off(pUmDevice); + netif_carrier_off(pUmDevice->dev); +#ifdef BCM_TASKLET + tasklet_kill(&pUmDevice->tasklet); +#endif + bcm5700_poll_wait(pUmDevice); + LM_Halt(pDevice); + pDevice->InitDone = 0; + bcm5700_free_remaining_rx_bufs(pUmDevice); +} + +void +bcm5700_free_remaining_rx_bufs(UM_DEVICE_BLOCK *pUmDevice) +{ + LM_DEVICE_BLOCK *pDevice = &pUmDevice->lm_dev; + UM_PACKET *pUmPacket; + int cnt, i; + + cnt = QQ_GetEntryCnt(&pUmDevice->rx_out_of_buf_q.Container); + for (i = 0; i < cnt; i++) { + if ((pUmPacket = + QQ_PopHead(&pUmDevice->rx_out_of_buf_q.Container)) + != 0) { + + MM_UnmapRxDma(pDevice, (LM_PACKET *) pUmPacket); + MM_FreeRxBuffer(pDevice, &pUmPacket->lm_packet); + QQ_PushTail(&pDevice->RxPacketFreeQ.Container, + pUmPacket); + } + } +} + +void +bcm5700_validate_param_range(UM_DEVICE_BLOCK *pUmDevice, int *param, + char *param_name, int min, int max, int deflt) +{ + if (((unsigned int) *param < (unsigned int) min) || + ((unsigned int) *param > (unsigned int) max)) { + + printk(KERN_WARNING "%s-%d: Invalid %s parameter (%u), using %u\n", bcm5700_driver, pUmDevice->index, param_name, (unsigned int) *param, (unsigned int) deflt); + *param = deflt; + } +} + +struct net_device * +bcm5700_find_peer(struct net_device *dev) +{ + struct net_device *tmp_dev; + UM_DEVICE_BLOCK *pUmDevice, *pUmTmp; + LM_DEVICE_BLOCK *pDevice; + + tmp_dev = 0; + pUmDevice = (UM_DEVICE_BLOCK *) dev->priv; + pDevice = &pUmDevice->lm_dev; + if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704) { + tmp_dev = root_tigon3_dev; + while (tmp_dev) { + pUmTmp = (PUM_DEVICE_BLOCK) tmp_dev->priv; + if ((tmp_dev != dev) && + (pUmDevice->pdev->bus->number == + pUmTmp->pdev->bus->number) && + PCI_SLOT(pUmDevice->pdev->devfn) == + PCI_SLOT(pUmTmp->pdev->devfn)) { + + break; + } + tmp_dev = pUmTmp->next_module; + } + } + return tmp_dev; +} + +LM_DEVICE_BLOCK * +MM_FindPeerDev(LM_DEVICE_BLOCK *pDevice) +{ + UM_DEVICE_BLOCK *pUmDevice = (UM_DEVICE_BLOCK *) pDevice; + struct net_device *dev = pUmDevice->dev; + struct net_device *peer_dev; + + peer_dev = bcm5700_find_peer(dev); + if (!peer_dev) + return 0; + return ((LM_DEVICE_BLOCK *) peer_dev->priv); +} + +#ifdef HAVE_POLL_CONTROLLER +STATIC void +poll_bcm5700(struct net_device *dev) +{ +#ifdef RED_HAT_LINUX_KERNEL + if (!netdump_mode) +#endif + { + disable_irq(dev->irq); + } + bcm5700_interrupt(dev->irq, dev, NULL); +#ifdef RED_HAT_LINUX_KERNEL + if (!netdump_mode) +#endif + { + enable_irq(dev->irq); + } +} +#endif diff -u --recursive --new-file linux-2.4.26/drivers/net/bcm/bits.h linux-2.4.26.patch/drivers/net/bcm/bits.h --- linux-2.4.26/drivers/net/bcm/bits.h 1969-12-31 16:00:00.000000000 -0800 +++ linux-2.4.26.patch/drivers/net/bcm/bits.h 2004-06-22 16:07:37.000000000 -0700 @@ -0,0 +1,61 @@ +/******************************************************************************/ +/* */ +/* Broadcom BCM5700 Linux Network Driver, Copyright (c) 2000 - 2003 Broadcom */ +/* Corporation. */ +/* All rights reserved. */ +/* */ +/* This program is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU General Public License as published by */ +/* the Free Software Foundation, located in the file LICENSE. */ +/* */ +/* History: */ +/* 02/25/00 Hav Khauv Initial version. */ +/******************************************************************************/ + +#ifndef BITS_H +#define BITS_H + + + +/******************************************************************************/ +/* Bit Mask definitions */ +/******************************************************************************/ + +#define BIT_NONE 0x00 +#define BIT_0 0x01 +#define BIT_1 0x02 +#define BIT_2 0x04 +#define BIT_3 0x08 +#define BIT_4 0x10 +#define BIT_5 0x20 +#define BIT_6 0x40 +#define BIT_7 0x80 +#define BIT_8 0x0100 +#define BIT_9 0x0200 +#define BIT_10 0x0400 +#define BIT_11 0x0800 +#define BIT_12 0x1000 +#define BIT_13 0x2000 +#define BIT_14 0x4000 +#define BIT_15 0x8000 +#define BIT_16 0x010000 +#define BIT_17 0x020000 +#define BIT_18 0x040000 +#define BIT_19 0x080000 +#define BIT_20 0x100000 +#define BIT_21 0x200000 +#define BIT_22 0x400000 +#define BIT_23 0x800000 +#define BIT_24 0x01000000 +#define BIT_25 0x02000000 +#define BIT_26 0x04000000 +#define BIT_27 0x08000000 +#define BIT_28 0x10000000 +#define BIT_29 0x20000000 +#define BIT_30 0x40000000 +#define BIT_31 0x80000000 + + + +#endif /* BITS_H */ + diff -u --recursive --new-file linux-2.4.26/drivers/net/bcm/fw_lso05.h linux-2.4.26.patch/drivers/net/bcm/fw_lso05.h --- linux-2.4.26/drivers/net/bcm/fw_lso05.h 1969-12-31 16:00:00.000000000 -0800 +++ linux-2.4.26.patch/drivers/net/bcm/fw_lso05.h 2004-06-22 16:07:37.000000000 -0700 @@ -0,0 +1,289 @@ +/******************************************************************************/ +/* */ +/* Broadcom BCM5700 Linux Network Driver, Copyright (c) 2000 - 2003 Broadcom */ +/* Corporation. */ +/* All rights reserved. */ +/* */ +/* This program is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU General Public License as published by */ +/* the Free Software Foundation, located in the file LICENSE. */ +/* */ +/* (c) COPYRIGHT 2001-2004 Broadcom Corporation, ALL RIGHTS RESERVED. */ +/* */ +/* Name: F W _ L S O 0 5. H */ +/* Author : Kevin Tran */ +/* Version: 1.2 */ +/* */ +/* Module Description: This file contains firmware binary code of TCP */ +/* Segmentation firmware (BCM5705). */ +/* */ +/* History: */ +/* 08/10/02 Kevin Tran Incarnation. */ +/* 02/02/04 Kevin Tran Added Support for BCM5788. */ +/******************************************************************************/ + +#ifndef __FW_LSO05_H__ +#define __FW_LSO05_H__ + +int t3StkOffLd05FwReleaseMajor = 0x1; +int t3StkOffLd05FwReleaseMinor = 0x2; +int t3StkOffLd05FwReleaseFix = 0x0; +U32 t3StkOffLd05FwStartAddr = 0x00010000; +U32 t3StkOffLd05FwTextAddr = 0x00010000; +int t3StkOffLd05FwTextLen = 0xe90; +U32 t3StkOffLd05FwRodataAddr = 0x00010e90; +int t3StkOffLd05FwRodataLen = 0x50; +U32 t3StkOffLd05FwDataAddr = 0x00010f00; +int t3StkOffLd05FwDataLen = 0x20; +U32 t3StkOffLd05FwSbssAddr = 0x00010f20; +int t3StkOffLd05FwSbssLen = 0x28; +U32 t3StkOffLd05FwBssAddr = 0x00010f50; +int t3StkOffLd05FwBssLen = 0x88; +U32 t3StkOffLd05FwText[(0xe90/4) + 1] = { +0xc004003, 0x0, 0x10f04, +0x0, 0x10000003, 0x0, 0xd, +0xd, 0x3c1d0001, 0x37bde000, 0x3a0f021, +0x3c100001, 0x26100000, 0xc004010, 0x0, +0xd, 0x27bdffe0, 0x3c04fefe, 0xafbf0018, +0xc0042e8, 0x34840002, 0xc004364, 0x0, +0x3c030001, 0x90630f34, 0x24020002, 0x3c040001, +0x24840e9c, 0x14620003, 0x24050001, 0x3c040001, +0x24840e90, 0x24060002, 0x3821, 0xafa00010, +0xc004378, 0xafa00014, 0xc00402c, 0x0, +0x8fbf0018, 0x3e00008, 0x27bd0020, 0x0, +0x0, 0x27bdffe0, 0xafbf001c, 0xafb20018, +0xafb10014, 0xc0042d4, 0xafb00010, 0x3c128000, +0x24110001, 0x8f706810, 0x32020400, 0x10400007, +0x0, 0x8f641008, 0x921024, 0x14400003, +0x0, 0xc004064, 0x0, 0x3c020001, +0x90420f56, 0x10510003, 0x32020200, 0x1040fff1, +0x0, 0xc0041b4, 0x0, 0x8004034, +0x0, 0x8fbf001c, 0x8fb20018, 0x8fb10014, +0x8fb00010, 0x3e00008, 0x27bd0020, 0x27bdffe0, +0x3c040001, 0x24840eb0, 0x2821, 0x3021, +0x3821, 0xafbf0018, 0xafa00010, 0xc004378, +0xafa00014, 0xd021, 0x24020130, 0xaf625000, +0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, +0x8fbf0018, 0x3e00008, 0x27bd0020, 0x0, +0x0, 0x3c030001, 0x24630f60, 0x90620000, +0x27bdfff0, 0x14400003, 0x80c021, 0x8004073, +0x4821, 0x3c022000, 0x3021024, 0x10400003, +0x24090002, 0x8004073, 0xa0600000, 0x24090001, +0x181040, 0x30431f80, 0x346f8008, 0x1520004b, +0x25eb0028, 0x3c040001, 0x832021, 0x8c848010, +0x3c050001, 0x24a50f7a, 0x41402, 0xa0a20000, +0x3c010001, 0xa0240f7b, 0x3c020001, 0x431021, +0x94428014, 0x3c010001, 0xa0220f7c, 0x3c0c0001, +0x1836021, 0x8d8c8018, 0x304200ff, 0x24420008, +0x220c3, 0x24020001, 0x3c010001, 0xa0220f60, +0x124102b, 0x1040000c, 0x3821, 0x24a6000e, +0x1602821, 0x8ca20000, 0x8ca30004, 0x24a50008, +0x24e70001, 0xacc20000, 0xacc30004, 0xe4102b, +0x1440fff8, 0x24c60008, 0x3821, 0x3c080001, +0x25080f7b, 0x91060000, 0x3c020001, 0x90420f7c, +0x2503000d, 0xc32821, 0x461023, 0x21fc2, +0x431021, 0x21043, 0x1840000c, 0x2021, +0x91020001, 0x461023, 0x21fc2, 0x431021, +0x21843, 0x94a20000, 0x24e70001, 0x822021, +0xe3102a, 0x1440fffb, 0x24a50002, 0x41c02, +0x3082ffff, 0x622021, 0x41402, 0x822021, +0x3c02ffff, 0x1821024, 0x3083ffff, 0x431025, +0x3c010001, 0x80040fa, 0xac220f80, 0x3c050001, +0x24a50f7c, 0x90a20000, 0x3c0c0001, 0x1836021, +0x8d8c8018, 0x220c2, 0x1080000e, 0x3821, +0x1603021, 0x24a5000c, 0x8ca20000, 0x8ca30004, +0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, +0xe4102b, 0x1440fff8, 0x24c60008, 0x3c050001, +0x24a50f7c, 0x90a20000, 0x30430007, 0x24020004, +0x10620011, 0x28620005, 0x10400005, 0x24020002, +0x10620008, 0x710c0, 0x80040fa, 0x0, +0x24020006, 0x1062000e, 0x710c0, 0x80040fa, +0x0, 0xa21821, 0x9463000c, 0x4b1021, +0x80040fa, 0xa4430000, 0x710c0, 0xa21821, +0x8c63000c, 0x4b1021, 0x80040fa, 0xac430000, +0xa21821, 0x8c63000c, 0x4b2021, 0xa21021, +0xac830000, 0x94420010, 0xa4820004, 0x95e70006, +0x3c020001, 0x90420f7c, 0x3c030001, 0x90630f7a, +0xe2c823, 0x3c020001, 0x90420f7b, 0x24630028, +0x1e34021, 0x24420028, 0x15200012, 0x1e23021, +0x94c2000c, 0x3c010001, 0xa4220f78, 0x94c20004, +0x94c30006, 0x3c010001, 0xa4200f76, 0x3c010001, +0xa4200f72, 0x21400, 0x431025, 0x3c010001, +0xac220f6c, 0x95020004, 0x3c010001, 0x8004124, +0xa4220f70, 0x3c020001, 0x94420f70, 0x3c030001, +0x94630f72, 0x431021, 0xa5020004, 0x3c020001, +0x94420f6c, 0xa4c20004, 0x3c020001, 0x8c420f6c, +0xa4c20006, 0x3c040001, 0x94840f72, 0x3c020001, +0x94420f70, 0x3c0a0001, 0x954a0f76, 0x441821, +0x3063ffff, 0x62182a, 0x24020002, 0x1122000b, +0x832023, 0x3c030001, 0x94630f78, 0x30620009, +0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, +0x94420f78, 0x30420009, 0x1425023, 0x24020001, +0x1122001b, 0x29220002, 0x50400005, 0x24020002, +0x11200007, 0x31a2ffff, 0x8004197, 0x0, +0x1122001d, 0x24020016, 0x8004197, 0x31a2ffff, +0x3c0e0001, 0x95ce0f80, 0x10800005, 0x1806821, +0x1c42021, 0x41c02, 0x3082ffff, 0x627021, +0xe1027, 0xa502000a, 0x3c030001, 0x90630f7b, +0x31a2ffff, 0xe21021, 0x800418d, 0x432023, +0x3c020001, 0x94420f80, 0x442021, 0x41c02, +0x3082ffff, 0x622021, 0x807021, 0x41027, +0x8004185, 0xa502000a, 0x3c050001, 0x24a50f7a, +0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, +0x90a20000, 0xe21023, 0xa5020002, 0x3c030001, +0x94630f80, 0x3c020001, 0x94420f5a, 0x30e5ffff, +0x641821, 0x451023, 0x622023, 0x41c02, +0x3082ffff, 0x622021, 0x41027, 0xa502000a, +0x3c030001, 0x90630f7c, 0x24620001, 0x14a20005, +0x807021, 0x1631021, 0x90420000, 0x8004185, +0x26200, 0x24620002, 0x14a20003, 0x306200fe, +0x4b1021, 0x944c0000, 0x3c020001, 0x94420f82, +0x3183ffff, 0x3c040001, 0x90840f7b, 0x431021, +0xe21021, 0x442023, 0x8a2021, 0x41c02, +0x3082ffff, 0x622021, 0x41402, 0x822021, +0x806821, 0x41027, 0xa4c20010, 0x31a2ffff, +0xe1c00, 0x431025, 0x3c040001, 0x24840f72, +0xade20010, 0x94820000, 0x3c050001, 0x94a50f76, +0x3c030001, 0x8c630f6c, 0x24420001, 0xb92821, +0xa4820000, 0x3322ffff, 0x622021, 0x83182b, +0x3c010001, 0xa4250f76, 0x10600003, 0x24a2ffff, +0x3c010001, 0xa4220f76, 0x3c024000, 0x3021025, +0x3c010001, 0xac240f6c, 0xaf621008, 0x3e00008, +0x27bd0010, 0x3c030001, 0x90630f56, 0x27bdffe8, +0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, +0x8f620cf4, 0x2442ffff, 0x3042007f, 0x21100, +0x8c434000, 0x3c010001, 0xac230f64, 0x8c434008, +0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, +0x24020088, 0x24020008, 0x3c010001, 0xa4220f68, +0x30620004, 0x10400005, 0x24020001, 0x3c010001, +0xa0220f57, 0x80041d5, 0x31402, 0x3c010001, +0xa0200f57, 0x31402, 0x3c010001, 0xa4220f54, +0x9483000c, 0x24020001, 0x3c010001, 0xa4200f50, +0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, +0x24020001, 0x1342001e, 0x0, 0x13400005, +0x24020003, 0x13420067, 0x0, 0x80042cf, +0x0, 0x3c020001, 0x94420f62, 0x241a0001, +0x3c010001, 0xa4200f5e, 0x3c010001, 0xa4200f52, +0x304407ff, 0x21bc2, 0x31823, 0x3063003e, +0x34630036, 0x21242, 0x3042003c, 0x621821, +0x3c010001, 0xa4240f58, 0x832021, 0x24630030, +0x3c010001, 0xa4240f5a, 0x3c010001, 0xa4230f5c, +0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, +0x3c040001, 0x94840f5a, 0x651021, 0x44102a, +0x10400013, 0x3c108000, 0xa31021, 0xa4c20000, +0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, +0x8f641008, 0x901024, 0x14400003, 0x0, +0xc004064, 0x0, 0x8f620cf4, 0x501024, +0x104000b7, 0x0, 0x800420f, 0x0, +0x3c030001, 0x94630f50, 0x851023, 0xa4c40000, +0x621821, 0x3042ffff, 0x3c010001, 0xa4230f50, +0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, +0xaf620cec, 0x94c30002, 0x3c020001, 0x94420f50, +0x14620012, 0x3c028000, 0x3c108000, 0x3c02a000, +0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, +0x901024, 0x14400003, 0x0, 0xc004064, +0x0, 0x8f620cf4, 0x501024, 0x1440fff7, +0x0, 0x80042cf, 0x241a0003, 0xaf620cf4, +0x3c108000, 0x8f641008, 0x901024, 0x14400003, +0x0, 0xc004064, 0x0, 0x8f620cf4, +0x501024, 0x1440fff7, 0x0, 0x80042cf, +0x241a0003, 0x3c070001, 0x24e70f50, 0x94e20000, +0x3821021, 0xaf620ce0, 0x3c020001, 0x8c420f64, +0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, +0x3c040001, 0x94840f58, 0x3c020001, 0x94420f5e, +0xa32823, 0x822023, 0x30a6ffff, 0x3083ffff, +0xc3102b, 0x14400043, 0x0, 0x3c020001, +0x94420f5c, 0x21400, 0x621025, 0xaf620ce8, +0x94e20000, 0x3c030001, 0x94630f54, 0x441021, +0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, +0x3c020001, 0x90420f57, 0x10400006, 0x3c03000c, +0x3c020001, 0x94420f68, 0x34630624, 0x800427c, +0xd021, 0x3c020001, 0x94420f68, 0x3c030008, +0x34630624, 0x431025, 0xaf620cec, 0x3c108000, +0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, +0x8f641008, 0x901024, 0x14400003, 0x0, +0xc004064, 0x0, 0x8f620cf4, 0x501024, +0x10400015, 0x0, 0x8004283, 0x0, +0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, +0x621825, 0x3c028000, 0xaf630cec, 0xaf620cf4, +0x8f641008, 0x901024, 0x14400003, 0x0, +0xc004064, 0x0, 0x8f620cf4, 0x501024, +0x1440fff7, 0x0, 0x3c010001, 0x80042cf, +0xa4200f5e, 0x3c020001, 0x94420f5c, 0x21400, +0xc21025, 0xaf620ce8, 0x3c020001, 0x90420f57, +0x10400009, 0x3c03000c, 0x3c020001, 0x94420f68, +0x34630624, 0xd021, 0x431025, 0xaf620cec, +0x80042c1, 0x3c108000, 0x3c020001, 0x94420f68, +0x3c030008, 0x34630604, 0x431025, 0xaf620cec, +0x3c020001, 0x94420f5e, 0x451021, 0x3c010001, +0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, +0x3c010001, 0xa0200f56, 0x8f641008, 0x901024, +0x14400003, 0x0, 0xc004064, 0x0, +0x8f620cf4, 0x501024, 0x1440fff7, 0x0, +0x8fbf0014, 0x8fb00010, 0x3e00008, 0x27bd0018, +0x0, 0x27bdffe0, 0x3c040001, 0x24840ec0, +0x2821, 0x3021, 0x3821, 0xafbf0018, +0xafa00010, 0xc004378, 0xafa00014, 0xd021, +0x24020130, 0xaf625000, 0x3c010001, 0xa4200f50, +0x3c010001, 0xa0200f57, 0x8fbf0018, 0x3e00008, +0x27bd0020, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, +0xafb00010, 0xaf60680c, 0x8f626804, 0x34420082, +0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, +0xac220f20, 0x24020b78, 0x3c010001, 0xac220f30, +0x34630002, 0xaf634000, 0xc004315, 0x808021, +0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, +0x14430005, 0x0, 0x3c020001, 0x8c420f20, +0x8004308, 0xac5000c0, 0x3c020001, 0x8c420f20, +0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, +0x3c010001, 0xac220f28, 0x3c010001, 0xac230f38, +0x3c010001, 0xac240f24, 0x8fbf0014, 0x8fb00010, +0x3e00008, 0x27bd0018, 0x3e00008, 0x24020001, +0x27bdfff8, 0x18800009, 0x2821, 0x8f63680c, +0x8f62680c, 0x1043fffe, 0x0, 0x24a50001, +0xa4102a, 0x1440fff9, 0x0, 0x3e00008, +0x27bd0008, 0x8f634450, 0x3c020001, 0x8c420f28, +0x31c02, 0x43102b, 0x14400008, 0x3c038000, +0x3c040001, 0x8c840f38, 0x8f624450, 0x21c02, +0x83102b, 0x1040fffc, 0x3c038000, 0xaf634444, +0x8f624444, 0x431024, 0x1440fffd, 0x0, +0x8f624448, 0x3e00008, 0x3042ffff, 0x3082ffff, +0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, +0x8004347, 0x2402ffff, 0x822025, 0xaf645c38, +0x8f625c30, 0x30420002, 0x1440fffc, 0x1021, +0x3e00008, 0x0, 0x8f624450, 0x3c030001, +0x8c630f24, 0x8004350, 0x3042ffff, 0x8f624450, +0x3042ffff, 0x43102b, 0x1440fffc, 0x0, +0x3e00008, 0x0, 0x27bdffe0, 0x802821, +0x3c040001, 0x24840ed0, 0x3021, 0x3821, +0xafbf0018, 0xafa00010, 0xc004378, 0xafa00014, +0x800435f, 0x0, 0x8fbf0018, 0x3e00008, +0x27bd0020, 0x3c020001, 0x3442d600, 0x3c030001, +0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, +0xac220f40, 0x24020040, 0x3c010001, 0xac220f44, +0x3c010001, 0xac200f3c, 0xac600000, 0x24630004, +0x83102b, 0x5040fffd, 0xac600000, 0x3e00008, +0x0, 0x804821, 0x8faa0010, 0x3c020001, +0x8c420f3c, 0x3c040001, 0x8c840f44, 0x8fab0014, +0x24430001, 0x44102b, 0x3c010001, 0xac230f3c, +0x14400003, 0x4021, 0x3c010001, 0xac200f3c, +0x3c020001, 0x8c420f3c, 0x3c030001, 0x8c630f40, +0x91240000, 0x21140, 0x431021, 0x481021, +0x25080001, 0xa0440000, 0x29020008, 0x1440fff4, +0x25290001, 0x3c020001, 0x8c420f3c, 0x3c030001, +0x8c630f40, 0x8f64680c, 0x21140, 0x431021, +0xac440008, 0xac45000c, 0xac460010, 0xac470014, +0xac4a0018, 0x3e00008, 0xac4b001c, 0x0, +0x0, 0x0 }; +U32 t3StkOffLd05FwRodata[(0x50/4) + 1] = { +0x4d61696e, +0x43707542, 0x0, 0x4d61696e, 0x43707541, +0x0, 0x0, 0x0, 0x73746b6f, +0x66666c64, 0x0, 0x0, 0x73746b6f, +0x66666c64, 0x0, 0x0, 0x66617461, +0x6c457272, 0x0, 0x0, 0x0 }; +U32 t3StkOffLd05FwData[(0x20/4) + 1] = { +0x0, +0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, +0x0, 0x0, 0x0, 0x0 }; + +#endif /* __FW_LSO05_H__ */ diff -u --recursive --new-file linux-2.4.26/drivers/net/bcm/fw_stkoffld.h linux-2.4.26.patch/drivers/net/bcm/fw_stkoffld.h --- linux-2.4.26/drivers/net/bcm/fw_stkoffld.h 1969-12-31 16:00:00.000000000 -0800 +++ linux-2.4.26.patch/drivers/net/bcm/fw_stkoffld.h 2004-06-22 16:07:37.000000000 -0700 @@ -0,0 +1,519 @@ +/******************************************************************************/ +/* */ +/* Broadcom BCM5700 Linux Network Driver, Copyright (c) 2000 - 2003 Broadcom */ +/* Corporation. */ +/* All rights reserved. */ +/* */ +/* This program is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU General Public License as published by */ +/* the Free Software Foundation, located in the file LICENSE. */ +/* */ +/* (c) COPYRIGHT 2000-2003 Broadcom Corporation, ALL RIGHTS RESERVED. */ +/* */ +/* Name: F W _ S T K O F F L D . H */ +/* Author : Kevin Tran */ +/* Version : 1.6 */ +/* */ +/* Module Description: This file contains firmware binary code of for TCP/IP */ +/* stack offload support. Currently, this firmware supports the following */ +/* features: */ +/* 1. TCP segmentation (aka Large Send Offload -- LSO) */ +/* 2. UDP Checksum offload support for IP fragmented UDP frames. */ +/* */ +/* History: */ +/* 07/17/01 Kevin Tran Incarnation. */ +/* 10/10/01 Kevin Tran Added UDP checksum offload support. */ +/* 10/20/01 Kevin Tran Fixed a problem where pseudo checksum is not */ +/* calculated correctly in case of IP */ +/* fragmentation case. */ +/* 10/30/01 Kevin Tran Fixed a problem where checksum is incorrectly */ +/* computed if bit BD_FLAG_TCP_UDP_CKSUM is set */ +/* in Send BDs. */ +/* 05/30/02 Kevin Tran Fixed a problem where UDP checksum is */ +/* incorrectly computed if the length of data is */ +/* less than 6 bytes in the last packetst of */ +/* of a chain of fragmented IP/UDP packets. */ +/* 12/01/02 Kevin Tran Fixed a problem where firmware might lockup */ +/* in a certain test scenario with BCM5704. */ +/* 12/10/02 Kevin Tran Fixed a problem where IP checksum might be */ +/* incorrectly calculated in some corner cases. */ +/* This problem should ONLY happen with BCM5702/ */ +/* BCM5703/BCM5704 ASICs. */ +/* 06/20/03 Kevin Tran Optimized performance so that pre-DMA code */ +/* doesn't have to wait until the first packet */ +/* is completely DMAed before it can setup DMAs */ +/* for subsequent packets. This requires host */ +/* driver to pass IP/TCP option lengths if any */ +/* to F/W via bit 15..12 of Send BD flag. */ +/* 08/12/03 Kevin Tran Fixed a problem where UDP checksum doesn't */ +/* work when the host driver seeds pseudo */ +/* checksum. */ +/* 12/24/03 Kevin Tran Fixed a problem where VLAN tag is not */ +/* inserted correctly in LSO mode. */ +/* 01/16/04 Kevin Tran Fixed a problem where Ethernet Type is not */ +/* set to 0x8870 when the outgoing LSO packet is */ +/* jumbo frame with SNAP encapsulation. */ +/******************************************************************************/ + +#ifndef __FW_STKOFFLD_H__ +#define __FW_STKOFFLD_H__ + +typedef LM_UINT32 U32; + +int t3StkOffLdFwReleaseMajor = 0x1; +int t3StkOffLdFwReleaseMinor = 0x6; +int t3StkOffLdFwReleaseFix = 0x0; +U32 t3StkOffLdFwStartAddr = 0x08000000; +U32 t3StkOffLdFwTextAddr = 0x08000000; +int t3StkOffLdFwTextLen = 0x1aa0; +U32 t3StkOffLdFwRodataAddr = 0x08001aa0; +int t3StkOffLdFwRodataLen = 0x60; +U32 t3StkOffLdFwDataAddr = 0x08001b20; +int t3StkOffLdFwDataLen = 0x30; +U32 t3StkOffLdFwSbssAddr = 0x08001b50; +int t3StkOffLdFwSbssLen = 0x2c; +U32 t3StkOffLdFwBssAddr = 0x08001b80; +int t3StkOffLdFwBssLen = 0x894; +U32 t3StkOffLdFwText[(0x1aa0/4) + 1] = { +0xe000003, 0x0, 0x8001b24, +0x0, 0x10000003, 0x0, 0xd, +0xd, 0x3c1d0800, 0x37bd4000, 0x3a0f021, +0x3c100800, 0x26100000, 0xe000010, 0x0, +0xd, 0x27bdffe0, 0x3c04fefe, 0xafbf0018, +0xe0005d8, 0x34840002, 0xe000668, 0x0, +0x3c030800, 0x90631b68, 0x24020002, 0x3c040800, +0x24841aac, 0x14620003, 0x24050001, 0x3c040800, +0x24841aa0, 0x24060006, 0x3821, 0xafa00010, +0xe00067c, 0xafa00014, 0x8f625c50, 0x34420001, +0xaf625c50, 0x8f625c90, 0x34420001, 0xaf625c90, +0x2402ffff, 0xe000034, 0xaf625404, 0x8fbf0018, +0x3e00008, 0x27bd0020, 0x0, 0x0, +0x0, 0x27bdffe0, 0xafbf001c, 0xafb20018, +0xafb10014, 0xe00005b, 0xafb00010, 0x24120002, +0x24110001, 0x8f706820, 0x32020100, 0x10400003, +0x0, 0xe0000bb, 0x0, 0x8f706820, +0x32022000, 0x10400004, 0x32020001, 0xe0001f0, +0x24040001, 0x32020001, 0x10400003, 0x0, +0xe0000a3, 0x0, 0x3c020800, 0x90421b98, +0x14520003, 0x0, 0xe0004c0, 0x0, +0xa00003c, 0xaf715028, 0x8fbf001c, 0x8fb20018, +0x8fb10014, 0x8fb00010, 0x3e00008, 0x27bd0020, +0x27bdffe0, 0x3c040800, 0x24841ac0, 0x2821, +0x3021, 0x3821, 0xafbf0018, 0xafa00010, +0xe00067c, 0xafa00014, 0x3c040800, 0x248423d8, +0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, +0xac201b9c, 0x3c010800, 0xac201ba0, 0x3c010800, +0xac201ba4, 0x3c010800, 0xac201bac, 0x3c010800, +0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, +0x3c010800, 0xac221b88, 0x8f624438, 0x3c010800, +0xac221b8c, 0x8f624410, 0xac80f7a8, 0x3c010800, +0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, +0xac2023c8, 0x3c010800, 0xac2023cc, 0x3c010800, +0xac202400, 0x3c010800, 0xac221b90, 0x8f620068, +0x24030007, 0x21702, 0x10430005, 0x0, +0x8f620068, 0x21702, 0x14400004, 0x24020001, +0x3c010800, 0xa000097, 0xac20240c, 0xac820034, +0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, +0x3021, 0x3821, 0xafa00010, 0xe00067c, +0xafa00014, 0x8fbf0018, 0x3e00008, 0x27bd0020, +0x27bdffe0, 0x3c040800, 0x24841ad8, 0x2821, +0x3021, 0x3821, 0xafbf0018, 0xafa00010, +0xe00067c, 0xafa00014, 0xe00005b, 0x0, +0xe0000b4, 0x2021, 0x8fbf0018, 0x3e00008, +0x27bd0020, 0x24020001, 0x8f636820, 0x821004, +0x21027, 0x621824, 0x3e00008, 0xaf636820, +0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, +0xafb40020, 0xafb3001c, 0xafb20018, 0xafb10014, +0xafb00010, 0x8f675c5c, 0x3c030800, 0x24631bbc, +0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, +0x90421b98, 0x14400119, 0x3c0200ff, 0x3442fff8, +0xe28824, 0xac670000, 0x111902, 0x306300ff, +0x30e20003, 0x211c0, 0x622825, 0xa04021, +0x71602, 0x3c030800, 0x90631b98, 0x3044000f, +0x14600036, 0x804821, 0x24020001, 0x3c010800, +0xa0221b98, 0x51100, 0x821025, 0x3c010800, +0xac201b9c, 0x3c010800, 0xac201ba0, 0x3c010800, +0xac201ba4, 0x3c010800, 0xac201bac, 0x3c010800, +0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, +0xac201bb4, 0x3c010800, 0xa42223d8, 0x9622000c, +0x30437fff, 0x3c010800, 0xa4222410, 0x30428000, +0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, +0x3c010800, 0xac2223f4, 0xa000102, 0x2406003e, +0x24060036, 0x3c010800, 0xac2023f4, 0x9622000a, +0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, +0x3c010800, 0xac2023f8, 0x21302, 0x21080, +0xc21021, 0x621821, 0x3c010800, 0xa42223d0, +0x3c010800, 0xa000115, 0xa4231b96, 0x9622000c, +0x3c010800, 0xa42223ec, 0x3c040800, 0x24841b9c, +0x8c820000, 0x21100, 0x3c010800, 0x220821, +0xac311bc8, 0x8c820000, 0x21100, 0x3c010800, +0x220821, 0xac271bcc, 0x8c820000, 0x25030001, +0x306601ff, 0x21100, 0x3c010800, 0x220821, +0xac261bd0, 0x8c820000, 0x21100, 0x3c010800, +0x220821, 0xac291bd4, 0x96230008, 0x3c020800, +0x8c421bac, 0x432821, 0x3c010800, 0xac251bac, +0x9622000a, 0x30420004, 0x14400018, 0x61100, +0x8f630c14, 0x3063000f, 0x2c620002, 0x1440000b, +0x3c02c000, 0x8f630c14, 0x3c020800, 0x8c421b40, +0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, +0x2c620002, 0x1040fff7, 0x3c02c000, 0xe21825, +0xaf635c5c, 0x8f625c50, 0x30420002, 0x10400014, +0x0, 0xa000147, 0x0, 0x3c030800, +0x8c631b80, 0x3c040800, 0x94841b94, 0x1221025, +0x3c010800, 0xa42223da, 0x24020001, 0x3c010800, +0xac221bb8, 0x24630001, 0x85202a, 0x3c010800, +0x10800003, 0xac231b80, 0x3c010800, 0xa4251b94, +0x3c060800, 0x24c61b9c, 0x8cc20000, 0x24420001, +0xacc20000, 0x28420080, 0x14400005, 0x0, +0xe000656, 0x24040002, 0xa0001e6, 0x0, +0x3c020800, 0x8c421bb8, 0x10400078, 0x24020001, +0x3c050800, 0x90a51b98, 0x14a20072, 0x0, +0x3c150800, 0x96b51b96, 0x3c040800, 0x8c841bac, +0x32a3ffff, 0x83102a, 0x1440006c, 0x0, +0x14830003, 0x0, 0x3c010800, 0xac2523f0, +0x1060005c, 0x9021, 0x24d60004, 0x60a021, +0x24d30014, 0x8ec20000, 0x28100, 0x3c110800, +0x2308821, 0xe000625, 0x8e311bc8, 0x402821, +0x10a00054, 0x0, 0x9628000a, 0x31020040, +0x10400005, 0x2407180c, 0x8e22000c, 0x2407188c, +0x21400, 0xaca20018, 0x3c030800, 0x701821, +0x8c631bd0, 0x3c020800, 0x501021, 0x8c421bd4, +0x31d00, 0x21400, 0x621825, 0xaca30014, +0x8ec30004, 0x96220008, 0x432023, 0x3242ffff, +0x3083ffff, 0x431021, 0x282102a, 0x14400002, +0x2b23023, 0x803021, 0x8e620000, 0x30c4ffff, +0x441021, 0xae620000, 0x8e220000, 0xaca20000, +0x8e220004, 0x8e63fff4, 0x431021, 0xaca20004, +0xa4a6000e, 0x8e62fff4, 0x441021, 0xae62fff4, +0x96230008, 0x43102a, 0x14400005, 0x2469021, +0x8e62fff0, 0xae60fff4, 0x24420001, 0xae62fff0, +0xaca00008, 0x3242ffff, 0x14540008, 0x24020305, +0x31020080, 0x54400001, 0x34e70010, 0x24020905, +0xa4a2000c, 0xa0001cb, 0x34e70020, 0xa4a2000c, +0x3c020800, 0x8c4223f0, 0x10400003, 0x3c024b65, +0xa0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, +0xaca2001c, 0x30e2ffff, 0xaca20010, 0xe0005a2, +0xa02021, 0x3242ffff, 0x54102b, 0x1440ffa9, +0x0, 0x24020002, 0x3c010800, 0xa0001e6, +0xa0221b98, 0x8ec2083c, 0x24420001, 0xa0001e6, +0xaec2083c, 0xe0004c0, 0x0, 0x8fbf002c, +0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, +0x8fb20018, 0x8fb10014, 0x8fb00010, 0x3e00008, +0x27bd0030, 0x27bdffd0, 0xafbf0028, 0xafb30024, +0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, +0x3c0200ff, 0x3442fff8, 0x3c070800, 0x24e71bb4, +0x2428824, 0x9623000e, 0x8ce20000, 0x431021, +0xace20000, 0x8e220010, 0x30420020, 0x14400011, +0x809821, 0xe00063b, 0x2202021, 0x3c02c000, +0x2421825, 0xaf635c9c, 0x8f625c90, 0x30420002, +0x1040011e, 0x0, 0xaf635c9c, 0x8f625c90, +0x30420002, 0x10400119, 0x0, 0xa00020d, +0x0, 0x8e240008, 0x8e230014, 0x41402, +0x231c0, 0x31502, 0x304201ff, 0x2442ffff, +0x3042007f, 0x31942, 0x30637800, 0x21100, +0x24424000, 0x624821, 0x9522000a, 0x3084ffff, +0x30420008, 0x104000b0, 0x429c0, 0x3c020800, +0x8c422400, 0x14400024, 0x24c50008, 0x94c20014, +0x3c010800, 0xa42223d0, 0x8cc40010, 0x41402, +0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, +0x94c2000e, 0x3083ffff, 0x431023, 0x3c010800, +0xac222408, 0x94c2001a, 0x3c010800, 0xac262400, +0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, +0x3c02c000, 0x2421825, 0xaf635c9c, 0x8f625c90, +0x30420002, 0x104000e5, 0x0, 0xaf635c9c, +0x8f625c90, 0x30420002, 0x104000e0, 0x0, +0xa000246, 0x0, 0x94c2000e, 0x3c030800, +0x946323d4, 0x434023, 0x3103ffff, 0x2c620008, +0x1040001c, 0x0, 0x94c20014, 0x24420028, +0xa22821, 0x31042, 0x1840000b, 0x2021, +0x24e60848, 0x403821, 0x94a30000, 0x8cc20000, +0x24840001, 0x431021, 0xacc20000, 0x87102a, +0x1440fff9, 0x24a50002, 0x31020001, 0x1040001f, +0x3c024000, 0x3c040800, 0x248423fc, 0xa0a00001, +0x94a30000, 0x8c820000, 0x431021, 0xa000285, +0xac820000, 0x8f626800, 0x3c030010, 0x431024, +0x10400009, 0x0, 0x94c2001a, 0x3c030800, +0x8c6323fc, 0x431021, 0x3c010800, 0xac2223fc, +0xa000286, 0x3c024000, 0x94c2001a, 0x94c4001c, +0x3c030800, 0x8c6323fc, 0x441023, 0x621821, +0x3c010800, 0xac2323fc, 0x3c024000, 0x2421825, +0xaf635c9c, 0x8f625c90, 0x30420002, 0x1440fffc, +0x0, 0x9522000a, 0x30420010, 0x1040009b, +0x0, 0x3c030800, 0x946323d4, 0x3c070800, +0x24e72400, 0x8ce40000, 0x8f626800, 0x24630030, +0x832821, 0x3c030010, 0x431024, 0x1440000a, +0x0, 0x94a20004, 0x3c040800, 0x8c842408, +0x3c030800, 0x8c6323fc, 0x441023, 0x621821, +0x3c010800, 0xac2323fc, 0x3c040800, 0x8c8423fc, +0x41c02, 0x3082ffff, 0x622021, 0x41402, +0x822021, 0x41027, 0xa4a20006, 0x3c030800, +0x8c632404, 0x3c0200ff, 0x3442fff8, 0x628824, +0x96220008, 0x24050001, 0x24034000, 0x231c0, +0x801021, 0xa4c2001a, 0xa4c0001c, 0xace00000, +0x3c010800, 0xac251b60, 0xaf635cb8, 0x8f625cb0, +0x30420002, 0x10400003, 0x0, 0x3c010800, +0xac201b60, 0x8e220008, 0xaf625cb8, 0x8f625cb0, +0x30420002, 0x10400003, 0x0, 0x3c010800, +0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, +0x0, 0x3c040800, 0xe00063b, 0x8c842404, +0xa00032a, 0x0, 0x3c030800, 0x90631b98, +0x24020002, 0x14620003, 0x3c034b65, 0xa0002e1, +0x8021, 0x8e22001c, 0x34637654, 0x10430002, +0x24100002, 0x24100001, 0xc02021, 0xe000350, +0x2003021, 0x24020003, 0x3c010800, 0xa0221b98, +0x24020002, 0x1202000a, 0x24020001, 0x3c030800, +0x8c6323f0, 0x10620006, 0x0, 0x3c020800, +0x944223d8, 0x21400, 0xa00031f, 0xae220014, +0x3c040800, 0x248423da, 0x94820000, 0x21400, +0xae220014, 0x3c020800, 0x8c421bbc, 0x3c03c000, +0x3c010800, 0xa0201b98, 0x431025, 0xaf625c5c, +0x8f625c50, 0x30420002, 0x10400009, 0x0, +0x2484f7e2, 0x8c820000, 0x431025, 0xaf625c5c, +0x8f625c50, 0x30420002, 0x1440fffa, 0x0, +0x3c020800, 0x24421b84, 0x8c430000, 0x24630001, +0xac430000, 0x8f630c14, 0x3063000f, 0x2c620002, +0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, +0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, +0xac221b40, 0x2c620002, 0x1040fff7, 0x0, +0x3c024000, 0x2421825, 0xaf635c9c, 0x8f625c90, +0x30420002, 0x1440fffc, 0x0, 0x12600003, +0x0, 0xe0004c0, 0x0, 0x8fbf0028, +0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, +0x3e00008, 0x27bd0030, 0x8f634450, 0x3c040800, +0x24841b88, 0x8c820000, 0x31c02, 0x43102b, +0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, +0x21c02, 0x83102b, 0x1040fffc, 0x3c038000, +0xaf634444, 0x8f624444, 0x431024, 0x1440fffd, +0x0, 0x8f624448, 0x3e00008, 0x3042ffff, +0x3c024000, 0x822025, 0xaf645c38, 0x8f625c30, +0x30420002, 0x1440fffc, 0x0, 0x3e00008, +0x0, 0x27bdffe0, 0x805821, 0x14c00011, +0x256e0008, 0x3c020800, 0x8c4223f4, 0x10400007, +0x24020016, 0x3c010800, 0xa42223d2, 0x2402002a, +0x3c010800, 0xa000364, 0xa42223d4, 0x8d670010, +0x71402, 0x3c010800, 0xa42223d2, 0x3c010800, +0xa42723d4, 0x3c040800, 0x948423d4, 0x3c030800, +0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, +0x832023, 0x1e2c023, 0x3065ffff, 0x24a20028, +0x1c24821, 0x3082ffff, 0x14c0001a, 0x1226021, +0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, +0x95820004, 0x95830006, 0x3c010800, 0xac2023e4, +0x3c010800, 0xac2023e8, 0x21400, 0x431025, +0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, +0xa4221bc4, 0x95230002, 0x1e51023, 0x43102a, +0x10400010, 0x24020001, 0x3c010800, 0xa000398, +0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, +0x94421bc4, 0x431021, 0xa5220004, 0x3c020800, +0x94421bc0, 0xa5820004, 0x3c020800, 0x8c421bc0, +0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, +0x8dad23e4, 0x3c0a0800, 0x144000e5, 0x8d4a23e8, +0x3c020800, 0x94421bc4, 0x4a1821, 0x3063ffff, +0x62182b, 0x24020002, 0x10c2000d, 0x1435023, +0x3c020800, 0x944223d6, 0x30420009, 0x10400008, +0x0, 0x9582000c, 0x3042fff6, 0xa582000c, +0x3c020800, 0x944223d6, 0x30420009, 0x1a26823, +0x3c020800, 0x8c4223f8, 0x1040004a, 0x1203821, +0x3c020800, 0x944223d2, 0x4021, 0xa520000a, +0x1e21023, 0xa5220002, 0x3082ffff, 0x21042, +0x18400008, 0x3021, 0x401821, 0x94e20000, +0x25080001, 0xc23021, 0x103102a, 0x1440fffb, +0x24e70002, 0x61c02, 0x30c2ffff, 0x623021, +0x61402, 0xc23021, 0xc02821, 0x61027, +0xa522000a, 0x3021, 0x2527000c, 0x4021, +0x94e20000, 0x25080001, 0xc23021, 0x2d020004, +0x1440fffb, 0x24e70002, 0x95220002, 0x4021, +0x91230009, 0x442023, 0x1803821, 0x3082ffff, +0xa4e00010, 0x621821, 0x21042, 0x18400010, +0xc33021, 0x404821, 0x94e20000, 0x24e70002, +0xc23021, 0x30e2007f, 0x14400006, 0x25080001, +0x8d630000, 0x3c02007f, 0x3442ff80, 0x625824, +0x25670008, 0x109102a, 0x1440fff3, 0x0, +0x30820001, 0x10400005, 0x61c02, 0xa0e00001, +0x94e20000, 0xc23021, 0x61c02, 0x30c2ffff, +0x623021, 0x61402, 0xc23021, 0xa00047d, +0x30c6ffff, 0x24020002, 0x14c20081, 0x0, +0x3c020800, 0x8c42240c, 0x14400007, 0x0, +0x3c020800, 0x944223d2, 0x95230002, 0x1e21023, +0x10620077, 0x0, 0x3c020800, 0x944223d2, +0x1e21023, 0xa5220002, 0x3c020800, 0x8c42240c, +0x1040001a, 0x31e3ffff, 0x8dc70010, 0x3c020800, +0x94421b96, 0xe04021, 0x72c02, 0xaa2021, +0x431023, 0x823823, 0x72402, 0x30e2ffff, +0x823821, 0x71027, 0xa522000a, 0x3102ffff, +0x3c040800, 0x948423d4, 0x453023, 0xe02821, +0x641823, 0x6d1821, 0xc33021, 0x61c02, +0x30c2ffff, 0xa00047d, 0x623021, 0x1203821, +0x4021, 0x3082ffff, 0x21042, 0x18400008, +0x3021, 0x401821, 0x94e20000, 0x25080001, +0xc23021, 0x103102a, 0x1440fffb, 0x24e70002, +0x61c02, 0x30c2ffff, 0x623021, 0x61402, +0xc23021, 0xc02821, 0x61027, 0xa522000a, +0x3021, 0x2527000c, 0x4021, 0x94e20000, +0x25080001, 0xc23021, 0x2d020004, 0x1440fffb, +0x24e70002, 0x95220002, 0x4021, 0x91230009, +0x442023, 0x1803821, 0x3082ffff, 0xa4e00010, +0x3c040800, 0x948423d4, 0x621821, 0xc33021, +0x61c02, 0x30c2ffff, 0x623021, 0x61c02, +0x3c020800, 0x944223d0, 0xc34821, 0x441023, +0x21fc2, 0x431021, 0x21043, 0x18400010, +0x3021, 0x402021, 0x94e20000, 0x24e70002, +0xc23021, 0x30e2007f, 0x14400006, 0x25080001, +0x8d630000, 0x3c02007f, 0x3442ff80, 0x625824, +0x25670008, 0x104102a, 0x1440fff3, 0x0, +0x3c020800, 0x944223ec, 0xc23021, 0x3122ffff, +0xc23021, 0x61c02, 0x30c2ffff, 0x623021, +0x61402, 0xc23021, 0xc04021, 0x61027, +0xa5820010, 0xadc00014, 0xa00049d, 0xadc00000, +0x8dc70010, 0xe04021, 0x11400007, 0x72c02, +0xaa3021, 0x61402, 0x30c3ffff, 0x433021, +0x61402, 0xc22821, 0x51027, 0xa522000a, +0x3c030800, 0x946323d4, 0x3102ffff, 0x1e21021, +0x433023, 0xcd3021, 0x61c02, 0x30c2ffff, +0x623021, 0x61402, 0xc23021, 0xc04021, +0x61027, 0xa5820010, 0x3102ffff, 0x51c00, +0x431025, 0xadc20010, 0x3c020800, 0x8c4223f4, +0x10400005, 0x2de205eb, 0x14400002, 0x25e2fff2, +0x34028870, 0xa5c20034, 0x3c030800, 0x246323e8, +0x8c620000, 0x24420001, 0xac620000, 0x3c040800, +0x8c8423e4, 0x3c020800, 0x8c421bc0, 0x3303ffff, +0x832021, 0x431821, 0x62102b, 0x3c010800, +0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, +0xac2223e4, 0x3c010800, 0xac231bc0, 0x3e00008, +0x27bd0020, 0x27bdffb8, 0x3c050800, 0x24a51b96, +0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, +0xafb50034, 0xafb40030, 0xafb3002c, 0xafb20028, +0xafb10024, 0xafb00020, 0x94a90000, 0x3c020800, +0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, +0x8c841bac, 0x1221023, 0x64182a, 0xa7a9001e, +0x106000be, 0xa7a20016, 0x24be0022, 0x97b6001e, +0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, +0x0, 0x8fc2fff8, 0x97a30016, 0x8fc4fff4, +0x431021, 0x82202a, 0x148000b0, 0x0, +0x97d50818, 0x32a2ffff, 0x104000a3, 0x9021, +0x40a021, 0x8821, 0xe000625, 0x0, +0x403021, 0x14c00007, 0x0, 0x3c020800, +0x8c4223dc, 0x24420001, 0x3c010800, 0xa000596, +0xac2223dc, 0x3c100800, 0x2118021, 0x8e101bc8, +0x9608000a, 0x31020040, 0x10400005, 0x2407180c, +0x8e02000c, 0x2407188c, 0x21400, 0xacc20018, +0x31020080, 0x54400001, 0x34e70010, 0x3c020800, +0x511021, 0x8c421bd0, 0x3c030800, 0x711821, +0x8c631bd4, 0x21500, 0x31c00, 0x431025, +0xacc20014, 0x96040008, 0x3242ffff, 0x821021, +0x282102a, 0x14400002, 0x2b22823, 0x802821, +0x8e020000, 0x2459021, 0xacc20000, 0x8e020004, +0xc02021, 0x26310010, 0xac820004, 0x30e2ffff, +0xac800008, 0xa485000e, 0xac820010, 0x24020305, +0xe0005a2, 0xa482000c, 0x3242ffff, 0x54102b, +0x1440ffc5, 0x3242ffff, 0xa00058e, 0x0, +0x8e620000, 0x8e63fffc, 0x43102a, 0x10400067, +0x0, 0x8e62fff0, 0x28900, 0x3c100800, +0x2118021, 0xe000625, 0x8e101bc8, 0x403021, +0x14c00005, 0x0, 0x8e62082c, 0x24420001, +0xa000596, 0xae62082c, 0x9608000a, 0x31020040, +0x10400005, 0x2407180c, 0x8e02000c, 0x2407188c, +0x21400, 0xacc20018, 0x3c020800, 0x511021, +0x8c421bd0, 0x3c030800, 0x711821, 0x8c631bd4, +0x21500, 0x31c00, 0x431025, 0xacc20014, +0x8e63fff4, 0x96020008, 0x432023, 0x3242ffff, +0x3083ffff, 0x431021, 0x2c2102a, 0x10400003, +0x802821, 0x97a9001e, 0x1322823, 0x8e620000, +0x30a4ffff, 0x441021, 0xae620000, 0xa4c5000e, +0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, +0x431021, 0xacc20004, 0x8e63fff4, 0x96020008, +0x641821, 0x62102a, 0x14400006, 0x2459021, +0x8e62fff0, 0xae60fff4, 0x24420001, 0xa000571, +0xae62fff0, 0xae63fff4, 0xacc00008, 0x3242ffff, +0x10560003, 0x31020004, 0x10400006, 0x24020305, +0x31020080, 0x54400001, 0x34e70010, 0x34e70020, +0x24020905, 0xa4c2000c, 0x8ee30000, 0x8ee20004, +0x14620007, 0x3c02b49a, 0x8ee20860, 0x54400001, +0x34e70400, 0x3c024b65, 0xa000588, 0x34427654, +0x344289ab, 0xacc2001c, 0x30e2ffff, 0xacc20010, +0xe0005a2, 0xc02021, 0x3242ffff, 0x56102b, +0x1440ff9b, 0x0, 0x8e620000, 0x8e63fffc, +0x43102a, 0x1440ff48, 0x0, 0x8fbf0044, +0x8fbe0040, 0x8fb7003c, 0x8fb60038, 0x8fb50034, +0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, +0x8fb00020, 0x3e00008, 0x27bd0048, 0x27bdffe8, +0xafbf0014, 0xafb00010, 0x8f624450, 0x8f634410, +0xa0005b1, 0x808021, 0x8f626820, 0x30422000, +0x10400003, 0x0, 0xe0001f0, 0x2021, +0x8f624450, 0x8f634410, 0x3042ffff, 0x43102b, +0x1440fff5, 0x0, 0x8f630c14, 0x3063000f, +0x2c620002, 0x1440000b, 0x0, 0x8f630c14, +0x3c020800, 0x8c421b40, 0x3063000f, 0x24420001, +0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, +0x0, 0xaf705c18, 0x8f625c10, 0x30420002, +0x10400009, 0x0, 0x8f626820, 0x30422000, +0x1040fff8, 0x0, 0xe0001f0, 0x2021, +0xa0005c4, 0x0, 0x8fbf0014, 0x8fb00010, +0x3e00008, 0x27bd0018, 0x0, 0x0, +0x0, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, +0xafb00010, 0xaf60680c, 0x8f626804, 0x34420082, +0xaf626804, 0x8f634000, 0x24020b50, 0x3c010800, +0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, +0x34630002, 0xaf634000, 0xe000605, 0x808021, +0x3c010800, 0xa0221b68, 0x304200ff, 0x24030002, +0x14430005, 0x0, 0x3c020800, 0x8c421b54, +0xa0005f8, 0xac5000c0, 0x3c020800, 0x8c421b54, +0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, +0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, +0x3c010800, 0xac241b58, 0x8fbf0014, 0x8fb00010, +0x3e00008, 0x27bd0018, 0x3c040800, 0x8c870000, +0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, +0x8cc20000, 0x14430007, 0x24050002, 0x3c0355aa, +0x346355aa, 0xac830000, 0x8cc20000, 0x50430001, +0x24050001, 0x3c020800, 0xac470000, 0x3e00008, +0xa01021, 0x27bdfff8, 0x18800009, 0x2821, +0x8f63680c, 0x8f62680c, 0x1043fffe, 0x0, +0x24a50001, 0xa4102a, 0x1440fff9, 0x0, +0x3e00008, 0x27bd0008, 0x8f634450, 0x3c020800, +0x8c421b5c, 0x31c02, 0x43102b, 0x14400008, +0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, +0x21c02, 0x83102b, 0x1040fffc, 0x3c038000, +0xaf634444, 0x8f624444, 0x431024, 0x1440fffd, +0x0, 0x8f624448, 0x3e00008, 0x3042ffff, +0x3082ffff, 0x2442e000, 0x2c422001, 0x14400003, +0x3c024000, 0xa000648, 0x2402ffff, 0x822025, +0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, +0x1021, 0x3e00008, 0x0, 0x8f624450, +0x3c030800, 0x8c631b58, 0xa000651, 0x3042ffff, +0x8f624450, 0x3042ffff, 0x43102b, 0x1440fffc, +0x0, 0x3e00008, 0x0, 0x27bdffe0, +0x802821, 0x3c040800, 0x24841af0, 0x3021, +0x3821, 0xafbf0018, 0xafa00010, 0xe00067c, +0xafa00014, 0xa000660, 0x0, 0x8fbf0018, +0x3e00008, 0x27bd0020, 0x0, 0x0, +0x0, 0x3c020800, 0x34423000, 0x3c030800, +0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, +0xac221b74, 0x24020040, 0x3c010800, 0xac221b78, +0x3c010800, 0xac201b70, 0xac600000, 0x24630004, +0x83102b, 0x5040fffd, 0xac600000, 0x3e00008, +0x0, 0x804821, 0x8faa0010, 0x3c020800, +0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, +0x24430001, 0x44102b, 0x3c010800, 0xac231b70, +0x14400003, 0x4021, 0x3c010800, 0xac201b70, +0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, +0x91240000, 0x21140, 0x431021, 0x481021, +0x25080001, 0xa0440000, 0x29020008, 0x1440fff4, +0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, +0x8c631b74, 0x8f64680c, 0x21140, 0x431021, +0xac440008, 0xac45000c, 0xac460010, 0xac470014, +0xac4a0018, 0x3e00008, 0xac4b001c, 0x0, +0x0, 0x0 }; +U32 t3StkOffLdFwRodata[(0x60/4) + 1] = { +0x4d61696e, +0x43707542, 0x0, 0x4d61696e, 0x43707541, +0x0, 0x0, 0x0, 0x73746b6f, +0x66666c64, 0x496e0000, 0x73746b6f, 0x66662a2a, +0x0, 0x53774576, 0x656e7430, 0x0, +0x0, 0x0, 0x0, 0x66617461, +0x6c457272, 0x0, 0x0, 0x0 }; +U32 t3StkOffLdFwData[(0x30/4) + 1] = { +0x0, 0x73746b6f, 0x66666c64, +0x5f76312e, 0x362e3000, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0 }; + +#endif /* __FW_STKOFFLD_H__ */ diff -u --recursive --new-file linux-2.4.26/drivers/net/bcm/lm.h linux-2.4.26.patch/drivers/net/bcm/lm.h --- linux-2.4.26/drivers/net/bcm/lm.h 1969-12-31 16:00:00.000000000 -0800 +++ linux-2.4.26.patch/drivers/net/bcm/lm.h 2004-06-22 16:07:37.000000000 -0700 @@ -0,0 +1,466 @@ +/******************************************************************************/ +/* */ +/* Broadcom BCM5700 Linux Network Driver, Copyright (c) 2000 - 2003 Broadcom */ +/* Corporation. */ +/* All rights reserved. */ +/* */ +/* This program is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU General Public License as published by */ +/* the Free Software Foundation, located in the file LICENSE. */ +/* */ +/* History: */ +/* 02/25/00 Hav Khauv Initial version. */ +/******************************************************************************/ + +#ifndef LM_H +#define LM_H + +#include "queue.h" +#include "bits.h" + + + +/******************************************************************************/ +/* Basic types. */ +/******************************************************************************/ + +typedef char LM_CHAR, *PLM_CHAR; +typedef unsigned int LM_UINT, *PLM_UINT; +typedef unsigned char LM_UINT8, *PLM_UINT8; +typedef unsigned short LM_UINT16, *PLM_UINT16; +typedef unsigned int LM_UINT32, *PLM_UINT32; +typedef unsigned int LM_COUNTER, *PLM_COUNTER; +typedef void LM_VOID, *PLM_VOID; +typedef char LM_BOOL, *PLM_BOOL; + +/* 64bit value. */ +typedef struct { +#ifdef BIG_ENDIAN_HOST + LM_UINT32 High; + LM_UINT32 Low; +#else /* BIG_ENDIAN_HOST */ + LM_UINT32 Low; + LM_UINT32 High; +#endif /* !BIG_ENDIAN_HOST */ +} LM_UINT64, *PLM_UINT64; + +typedef LM_UINT64 LM_PHYSICAL_ADDRESS, *PLM_PHYSICAL_ADDRESS; + +/* void LM_INC_PHYSICAL_ADDRESS(PLM_PHYSICAL_ADDRESS pAddr,LM_UINT32 IncSize) */ +#define LM_INC_PHYSICAL_ADDRESS(pAddr, IncSize) \ + { \ + LM_UINT32 OrgLow; \ + \ + OrgLow = (pAddr)->Low; \ + (pAddr)->Low += IncSize; \ + if((pAddr)->Low < OrgLow) { \ + (pAddr)->High++; /* Wrap around. */ \ + } \ + } + + +#ifndef TRUE +#define TRUE 1 +#endif /* TRUE */ + +#ifndef FALSE +#define FALSE 0 +#endif /* FALSE */ + +#ifndef NULL +#define NULL ((void *) 0) +#endif /* NULL */ + +#ifndef OFFSETOF +#define OFFSETOF(_s, _m) (MM_UINT_PTR(&(((_s *) 0)->_m))) +#endif /* OFFSETOF */ + + + +/******************************************************************************/ +/* Simple macros. */ +/******************************************************************************/ + +#define IS_ETH_BROADCAST(_pEthAddr) \ + (((unsigned char *) (_pEthAddr))[0] == ((unsigned char) 0xff)) + +#define IS_ETH_MULTICAST(_pEthAddr) \ + (((unsigned char *) (_pEthAddr))[0] & ((unsigned char) 0x01)) + +#define IS_ETH_ADDRESS_EQUAL(_pEtherAddr1, _pEtherAddr2) \ + ((((unsigned char *) (_pEtherAddr1))[0] == \ + ((unsigned char *) (_pEtherAddr2))[0]) && \ + (((unsigned char *) (_pEtherAddr1))[1] == \ + ((unsigned char *) (_pEtherAddr2))[1]) && \ + (((unsigned char *) (_pEtherAddr1))[2] == \ + ((unsigned char *) (_pEtherAddr2))[2]) && \ + (((unsigned char *) (_pEtherAddr1))[3] == \ + ((unsigned char *) (_pEtherAddr2))[3]) && \ + (((unsigned char *) (_pEtherAddr1))[4] == \ + ((unsigned char *) (_pEtherAddr2))[4]) && \ + (((unsigned char *) (_pEtherAddr1))[5] == \ + ((unsigned char *) (_pEtherAddr2))[5])) + +#define COPY_ETH_ADDRESS(_Src, _Dst) \ + ((unsigned char *) (_Dst))[0] = ((unsigned char *) (_Src))[0]; \ + ((unsigned char *) (_Dst))[1] = ((unsigned char *) (_Src))[1]; \ + ((unsigned char *) (_Dst))[2] = ((unsigned char *) (_Src))[2]; \ + ((unsigned char *) (_Dst))[3] = ((unsigned char *) (_Src))[3]; \ + ((unsigned char *) (_Dst))[4] = ((unsigned char *) (_Src))[4]; \ + ((unsigned char *) (_Dst))[5] = ((unsigned char *) (_Src))[5]; + + + +/******************************************************************************/ +/* Constants. */ +/******************************************************************************/ + +#define ETHERNET_ADDRESS_SIZE 6 +#define ETHERNET_PACKET_HEADER_SIZE 14 +#define MIN_ETHERNET_PACKET_SIZE 64 /* with 4 byte crc. */ +#define MAX_ETHERNET_PACKET_SIZE 1518 /* with 4 byte crc. */ +#define MIN_ETHERNET_PACKET_SIZE_NO_CRC 60 +#define MAX_ETHERNET_PACKET_SIZE_NO_CRC 1514 +#define MAX_ETHERNET_PACKET_BUFFER_SIZE 1536 /* A nice even number. */ +#define MAX_ETHERNET_JUMBO_PACKET_SIZE_NO_CRC 9014 + +#ifndef LM_MAX_MC_TABLE_SIZE +#define LM_MAX_MC_TABLE_SIZE 32 +#endif /* LM_MAX_MC_TABLE_SIZE */ +#define LM_MC_ENTRY_SIZE (ETHERNET_ADDRESS_SIZE+1) +#define LM_MC_INSTANCE_COUNT_INDEX (LM_MC_ENTRY_SIZE-1) + + +/* Receive filter masks. */ +#define LM_ACCEPT_UNICAST 0x0001 +#define LM_ACCEPT_MULTICAST 0x0002 +#define LM_ACCEPT_ALL_MULTICAST 0x0004 +#define LM_ACCEPT_BROADCAST 0x0008 +#define LM_ACCEPT_ERROR_PACKET 0x0010 +#define LM_KEEP_VLAN_TAG 0x0020 + +#define LM_PROMISCUOUS_MODE 0x10000 + + + +/******************************************************************************/ +/* PCI registers. */ +/******************************************************************************/ + +#define PCI_VENDOR_ID_REG 0x00 +#define PCI_DEVICE_ID_REG 0x02 + +#define PCI_COMMAND_REG 0x04 +#define PCI_IO_SPACE_ENABLE 0x0001 +#define PCI_MEM_SPACE_ENABLE 0x0002 +#define PCI_BUSMASTER_ENABLE 0x0004 +#define PCI_MEMORY_WRITE_INVALIDATE 0x0010 +#define PCI_PARITY_ERROR_ENABLE 0x0040 +#define PCI_SYSTEM_ERROR_ENABLE 0x0100 +#define PCI_FAST_BACK_TO_BACK_ENABLE 0x0200 + +#define PCI_STATUS_REG 0x06 +#define PCI_REV_ID_REG 0x08 + +#define PCI_CACHE_LINE_SIZE_REG 0x0c + +#define PCI_IO_BASE_ADDR_REG 0x10 +#define PCI_IO_BASE_ADDR_MASK 0xfffffff0 + +#define PCI_MEM_BASE_ADDR_LOW 0x10 +#define PCI_MEM_BASE_ADDR_HIGH 0x14 + +#define PCI_SUBSYSTEM_VENDOR_ID_REG 0x2c +#define PCI_SUBSYSTEM_ID_REG 0x2e +#define PCI_INT_LINE_REG 0x3c + +#define PCIX_CAP_REG 0x40 +#define PCIX_ENABLE_RELAXED_ORDERING BIT_17 + +/******************************************************************************/ +/* Fragment structure. */ +/******************************************************************************/ + +typedef struct { + LM_UINT32 FragSize; + LM_PHYSICAL_ADDRESS FragBuf; +} LM_FRAG, *PLM_FRAG; + +typedef struct { + /* FragCount is initialized for the caller to the maximum array size, on */ + /* return FragCount is the number of the actual fragments in the array. */ + LM_UINT32 FragCount; + + /* Total buffer size. */ + LM_UINT32 TotalSize; + + /* Fragment array buffer. */ + LM_FRAG Fragments[1]; +} LM_FRAG_LIST, *PLM_FRAG_LIST; + +#define DECLARE_FRAG_LIST_BUFFER_TYPE(_FRAG_LIST_TYPE_NAME, _MAX_FRAG_COUNT) \ + typedef struct { \ + LM_FRAG_LIST FragList; \ + LM_FRAG FragListBuffer[_MAX_FRAG_COUNT-1]; \ + } _FRAG_LIST_TYPE_NAME, *P##_FRAG_LIST_TYPE_NAME + + + +/******************************************************************************/ +/* Status codes. */ +/******************************************************************************/ + +#define LM_STATUS_SUCCESS 0 +#define LM_STATUS_FAILURE 1 + +#define LM_STATUS_INTERRUPT_ACTIVE 2 +#define LM_STATUS_INTERRUPT_NOT_ACTIVE 3 + +#define LM_STATUS_LINK_ACTIVE 4 +#define LM_STATUS_LINK_DOWN 5 +#define LM_STATUS_LINK_SETTING_MISMATCH 6 + +#define LM_STATUS_TOO_MANY_FRAGMENTS 7 +#define LM_STATUS_TRANSMIT_ABORTED 8 +#define LM_STATUS_TRANSMIT_ERROR 9 +#define LM_STATUS_RECEIVE_ABORTED 10 +#define LM_STATUS_RECEIVE_ERROR 11 +#define LM_STATUS_INVALID_PACKET_SIZE 12 +#define LM_STATUS_OUT_OF_MAP_REGISTERS 13 +#define LM_STATUS_UNKNOWN_ADAPTER 14 + +typedef LM_UINT LM_STATUS, *PLM_STATUS; + + +/******************************************************************************/ +/* Line speed. */ +/******************************************************************************/ + +#define LM_LINE_SPEED_UNKNOWN 0 +#define LM_LINE_SPEED_AUTO LM_LINE_SPEED_UNKNOWN +#define LM_LINE_SPEED_10MBPS 10 +#define LM_LINE_SPEED_100MBPS 100 +#define LM_LINE_SPEED_1000MBPS 1000 + +typedef LM_UINT32 LM_LINE_SPEED, *PLM_LINE_SPEED; + + + +/******************************************************************************/ +/* Duplex mode. */ +/******************************************************************************/ + +#define LM_DUPLEX_MODE_UNKNOWN 0 +#define LM_DUPLEX_MODE_HALF 1 +#define LM_DUPLEX_MODE_FULL 2 + +typedef LM_UINT32 LM_DUPLEX_MODE, *PLM_DUPLEX_MODE; + + + +/******************************************************************************/ +/* Power state. */ +/******************************************************************************/ + +#define LM_POWER_STATE_D0 0 +#define LM_POWER_STATE_D1 1 +#define LM_POWER_STATE_D2 2 +#define LM_POWER_STATE_D3 3 + +typedef LM_UINT32 LM_POWER_STATE, *PLM_POWER_STATE; + + + +/******************************************************************************/ +/* Task offloading. */ +/******************************************************************************/ + +#define LM_TASK_OFFLOAD_NONE 0x0000 +#define LM_TASK_OFFLOAD_TX_IP_CHECKSUM 0x0001 +#define LM_TASK_OFFLOAD_RX_IP_CHECKSUM 0x0002 +#define LM_TASK_OFFLOAD_TX_TCP_CHECKSUM 0x0004 +#define LM_TASK_OFFLOAD_RX_TCP_CHECKSUM 0x0008 +#define LM_TASK_OFFLOAD_TX_UDP_CHECKSUM 0x0010 +#define LM_TASK_OFFLOAD_RX_UDP_CHECKSUM 0x0020 +#define LM_TASK_OFFLOAD_TCP_SEGMENTATION 0x0040 + +typedef LM_UINT32 LM_TASK_OFFLOAD, *PLM_TASK_OFFLOAD; + + + +/******************************************************************************/ +/* Flow control. */ +/******************************************************************************/ + +#define LM_FLOW_CONTROL_NONE 0x00 +#define LM_FLOW_CONTROL_RECEIVE_PAUSE 0x01 +#define LM_FLOW_CONTROL_TRANSMIT_PAUSE 0x02 +#define LM_FLOW_CONTROL_RX_TX_PAUSE (LM_FLOW_CONTROL_RECEIVE_PAUSE | \ + LM_FLOW_CONTROL_TRANSMIT_PAUSE) + +/* This value can be or-ed with RECEIVE_PAUSE and TRANSMIT_PAUSE. If the */ +/* auto-negotiation is disabled and the RECEIVE_PAUSE and TRANSMIT_PAUSE */ +/* bits are set, then flow control is enabled regardless of link partner's */ +/* flow control capability. */ +#define LM_FLOW_CONTROL_AUTO_PAUSE 0x80000000 + +typedef LM_UINT32 LM_FLOW_CONTROL, *PLM_FLOW_CONTROL; + + + +/******************************************************************************/ +/* Wake up mode. */ +/******************************************************************************/ + +#define LM_WAKE_UP_MODE_NONE 0 +#define LM_WAKE_UP_MODE_MAGIC_PACKET 1 +#define LM_WAKE_UP_MODE_NWUF 2 +#define LM_WAKE_UP_MODE_LINK_CHANGE 4 + +typedef LM_UINT32 LM_WAKE_UP_MODE, *PLM_WAKE_UP_MODE; + + + +/******************************************************************************/ +/* Counters. */ +/******************************************************************************/ + +#define LM_COUNTER_FRAMES_XMITTED_OK 0 +#define LM_COUNTER_FRAMES_RECEIVED_OK 1 +#define LM_COUNTER_ERRORED_TRANSMIT_COUNT 2 +#define LM_COUNTER_ERRORED_RECEIVE_COUNT 3 +#define LM_COUNTER_RCV_CRC_ERROR 4 +#define LM_COUNTER_ALIGNMENT_ERROR 5 +#define LM_COUNTER_SINGLE_COLLISION_FRAMES 6 +#define LM_COUNTER_MULTIPLE_COLLISION_FRAMES 7 +#define LM_COUNTER_FRAMES_DEFERRED 8 +#define LM_COUNTER_MAX_COLLISIONS 9 +#define LM_COUNTER_RCV_OVERRUN 10 +#define LM_COUNTER_XMIT_UNDERRUN 11 +#define LM_COUNTER_UNICAST_FRAMES_XMIT 12 +#define LM_COUNTER_MULTICAST_FRAMES_XMIT 13 +#define LM_COUNTER_BROADCAST_FRAMES_XMIT 14 +#define LM_COUNTER_UNICAST_FRAMES_RCV 15 +#define LM_COUNTER_MULTICAST_FRAMES_RCV 16 +#define LM_COUNTER_BROADCAST_FRAMES_RCV 17 + +typedef LM_UINT32 LM_COUNTER_TYPE, *PLM_COUNTER_TYPE; + + +typedef LM_UINT32 LM_RESET_TYPE; +#define LM_SHUTDOWN_RESET 0 +#define LM_INIT_RESET 1 +#define LM_SUSPEND_RESET 2 + +/******************************************************************************/ +/* Forward definition. */ +/******************************************************************************/ + +typedef struct _LM_DEVICE_BLOCK *PLM_DEVICE_BLOCK; +typedef struct _LM_PACKET *PLM_PACKET; + + + +/******************************************************************************/ +/* Function prototypes. */ +/******************************************************************************/ + +LM_STATUS LM_GetAdapterInfo(PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_InitializeAdapter(PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_ResetAdapter(PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_DisableInterrupt(PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_EnableInterrupt(PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_SendPacket(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket); +LM_STATUS LM_ServiceInterrupts(PLM_DEVICE_BLOCK pDevice); +#ifdef BCM_NAPI_RXPOLL +int LM_ServiceRxPoll(PLM_DEVICE_BLOCK pDevice, int limit); +#endif +LM_STATUS LM_QueueRxPackets(PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_SetReceiveMask(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Mask); +LM_STATUS LM_Halt(PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_Abort(PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_MulticastAdd(PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pMcAddress); +LM_STATUS LM_MulticastDel(PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pMcAddress); +LM_STATUS LM_MulticastClear(PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_SetMacAddress(PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pMacAddress); +LM_STATUS LM_LoopbackAddress(PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pAddress); + +LM_UINT32 LM_GetCrcCounter(PLM_DEVICE_BLOCK pDevice); + +LM_WAKE_UP_MODE LM_PMCapabilities(PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_NwufAdd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 ByteMaskSize, + LM_UINT8 *pByteMask, LM_UINT8 *pPattern); +LM_STATUS LM_NwufRemove(PLM_DEVICE_BLOCK pDevice, LM_UINT32 ByteMaskSize, + LM_UINT8 *pByteMask, LM_UINT8 *pPattern); +LM_STATUS LM_SetPowerState(PLM_DEVICE_BLOCK pDevice, LM_POWER_STATE PowerLevel); + +LM_VOID LM_ReadPhy(PLM_DEVICE_BLOCK pDevice, LM_UINT32 PhyReg, + PLM_UINT32 pData32); +LM_VOID LM_WritePhy(PLM_DEVICE_BLOCK pDevice, LM_UINT32 PhyReg, + LM_UINT32 Data32); + +LM_STATUS LM_EnableMacLoopBack(PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_DisableMacLoopBack(PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_EnablePhyLoopBack(PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_DisablePhyLoopBack(PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_EnableExtLoopBack(PLM_DEVICE_BLOCK pDevice, LM_LINE_SPEED Speed); +LM_STATUS LM_DisableExtLoopBack(PLM_DEVICE_BLOCK pDevice); + +LM_STATUS LM_SetupPhy(PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_BlinkLED(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlinkDuration); +LM_STATUS LM_GetStats(PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_NvramRead(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset, + LM_UINT32 *pData); +LM_STATUS LM_NvramWriteBlock(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset, + LM_UINT32 *pData, LM_UINT32 Size); +LM_VOID LM_ResetPhy(PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_ShutdownChip(PLM_DEVICE_BLOCK pDevice, LM_RESET_TYPE Mode); +LM_STATUS LM_HaltCpu(PLM_DEVICE_BLOCK pDevice,LM_UINT32 cpu_number); +LM_UINT32 ComputeCrc32(LM_UINT8 *pBuffer, LM_UINT32 BufferSize); +LM_STATUS LM_SwitchClocks(PLM_DEVICE_BLOCK pDevice); + + + +/******************************************************************************/ +/* These are the OS specific functions called by LMAC. */ +/******************************************************************************/ + +LM_STATUS MM_ReadConfig16(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset, + LM_UINT16 *pValue16); +LM_STATUS MM_WriteConfig16(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset, + LM_UINT16 Value16); +LM_STATUS MM_ReadConfig32(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset, + LM_UINT32 *pValue32); +LM_STATUS MM_WriteConfig32(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset, + LM_UINT32 Value32); +LM_STATUS MM_MapMemBase(PLM_DEVICE_BLOCK pDevice); +LM_STATUS MM_MapIoBase(PLM_DEVICE_BLOCK pDevice); +LM_STATUS MM_IndicateRxPackets(PLM_DEVICE_BLOCK pDevice); +LM_STATUS MM_IndicateTxPackets(PLM_DEVICE_BLOCK pDevice); +LM_STATUS MM_StartTxDma(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket); +LM_STATUS MM_CompleteTxDma(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket); +LM_STATUS MM_AllocateMemory(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlockSize, + PLM_VOID *pMemoryBlockVirt); +LM_STATUS MM_AllocateSharedMemory(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlockSize, + PLM_VOID *pMemoryBlockVirt, PLM_PHYSICAL_ADDRESS pMemoryBlockPhy, + LM_BOOL Cached); +LM_STATUS MM_GetConfig(PLM_DEVICE_BLOCK pDevice); +LM_STATUS MM_IndicateStatus(PLM_DEVICE_BLOCK pDevice, LM_STATUS Status); +LM_STATUS MM_InitializeUmPackets(PLM_DEVICE_BLOCK pDevice); +LM_STATUS MM_FreeRxBuffer(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket); +LM_STATUS MM_CoalesceTxBuffer(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket); +PLM_DEVICE_BLOCK MM_FindPeerDev(PLM_DEVICE_BLOCK pDevice); +LM_VOID MM_UnmapRxDma(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket); +#ifdef BCM_NAPI_RXPOLL +LM_STATUS MM_ScheduleRxPoll(PLM_DEVICE_BLOCK pDevice); +#endif +LM_STATUS MM_Sleep(PLM_DEVICE_BLOCK pDevice, LM_UINT32 msec); +LM_STATUS LM_MbufWorkAround(PLM_DEVICE_BLOCK pDevice); + +#if INCLUDE_5703_A0_FIX +LM_STATUS LM_Load5703DmaWFirmware(PLM_DEVICE_BLOCK pDevice); +#endif + + +#endif /* LM_H */ + diff -u --recursive --new-file linux-2.4.26/drivers/net/bcm/Makefile linux-2.4.26.patch/drivers/net/bcm/Makefile --- linux-2.4.26/drivers/net/bcm/Makefile 1969-12-31 16:00:00.000000000 -0800 +++ linux-2.4.26.patch/drivers/net/bcm/Makefile 2004-06-10 09:58:19.000000000 -0700 @@ -0,0 +1,13 @@ + +# +# Makefile for linux/drivers/net/bcm +# + +O_TARGET := bcm5700.o +obj-y := b57um.o b57proc.o tigon3.o autoneg.o 5701rls.o tcp_seg.o b57diag.o +obj-m := $(O_TARGET) + +EXTRA_CFLAGS = -DDBG=0 -DT3_JUMBO_RCV_RCB_ENTRY_COUNT=256 -DNICE_SUPPORT -DPCIX_TARGET_WORKAROUND=1 -DINCLUDE_TBI_SUPPORT -DINCLUDE_5701_AX_FIX=1 + +include $(TOPDIR)/Rules.make + diff -u --recursive --new-file linux-2.4.26/drivers/net/bcm/mm.h linux-2.4.26.patch/drivers/net/bcm/mm.h --- linux-2.4.26/drivers/net/bcm/mm.h 1969-12-31 16:00:00.000000000 -0800 +++ linux-2.4.26.patch/drivers/net/bcm/mm.h 2004-06-22 16:07:37.000000000 -0700 @@ -0,0 +1,569 @@ +/******************************************************************************/ +/* */ +/* Broadcom BCM5700 Linux Network Driver, Copyright (c) 2000 - 2003 Broadcom */ +/* Corporation. */ +/* All rights reserved. */ +/* */ +/* This program is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU General Public License as published by */ +/* the Free Software Foundation, located in the file LICENSE. */ +/* */ +/******************************************************************************/ + +#ifndef MM_H +#define MM_H + +#include +#if defined(CONFIG_SMP) && ! defined(__SMP__) +#define __SMP__ +#endif +#if defined(CONFIG_MODVERSIONS) && defined(MODULE) && ! defined(MODVERSIONS) +#define MODVERSIONS +#endif + +#ifndef B57UM +#define __NO_VERSION__ +#endif +#include +#ifdef MODULE +#if defined(MODVERSIONS) && (LINUX_VERSION_CODE < 0x020500) +#include +#endif +#include +#else +#define MOD_INC_USE_COUNT +#define MOD_DEC_USE_COUNT +#define SET_MODULE_OWNER(dev) +#define MODULE_DEVICE_TABLE(pci, pci_tbl) +#endif + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include /* Processor type for cache alignment. */ +#include +#include +#include +#include +#include +#include +#include +#if (LINUX_VERSION_CODE >= 0x020400) +#if (LINUX_VERSION_CODE < 0x020500) +#include +#endif +#include +#endif +#ifdef CONFIG_PROC_FS +#include +#include +#define BCM_PROC_FS 1 +#endif +#ifdef NETIF_F_HW_VLAN_TX +#include +#define BCM_VLAN 1 +#endif +#ifdef NETIF_F_TSO +#define BCM_TSO 1 +#define INCLUDE_TCP_SEG_SUPPORT 1 +#include +#include +#include +#endif + +#if (LINUX_VERSION_CODE >= 0x020400) +#ifndef ETHTOOL_GEEPROM + +#define ETHTOOL_GEEPROM 0x0000000b /* Get EEPROM data */ +#define ETHTOOL_SEEPROM 0x0000000c /* Set EEPROM data */ + +/* for passing EEPROM chunks */ +struct ethtool_eeprom { + u32 cmd; + u32 magic; + u32 offset; /* in bytes */ + u32 len; /* in bytes */ + u8 data[0]; +}; +#define BCM_EEDUMP_LEN(info_p, size) *((u32 *) &((info_p)->reserved1[24]))=size + +#else + +#define BCM_EEDUMP_LEN(info_p, size) (info_p)->eedump_len=size + +#endif +#endif + +#define BCM_INT_COAL 1 +#define BCM_NIC_SEND_BD 1 +#define BCM_ASF 1 +#define BCM_WOL 1 +#define BCM_TASKLET 1 + +#define INCLUDE_5750_A0_FIX 1 + +#if HAVE_NETIF_RECEIVE_SKB +#define BCM_NAPI_RXPOLL 1 +#undef BCM_TASKLET +#endif + +#if defined(CONFIG_PPC64) +#define BCM_DISCONNECT_AT_CACHELINE 1 +#endif + +#ifdef BCM_SMALL_DRV +#undef BCM_PROC_FS +#undef ETHTOOL_GEEPROM +#undef ETHTOOL_SEEPROM +#undef ETHTOOL_GREGS +#undef ETHTOOL_GPAUSEPARAM +#undef ETHTOOL_GRXCSUM +#undef ETHTOOL_TEST +#undef BCM_INT_COAL +#undef BCM_NIC_SEND_BD +#undef BCM_WOL +#undef NICE_SUPPORT +#undef BCM_TASKLET +#undef BCM_TSO +#endif + +#ifdef __BIG_ENDIAN +#define BIG_ENDIAN_HOST 1 +#endif + +#define MM_SWAP_LE32(x) cpu_to_le32(x) +#define MM_SWAP_BE32(x) cpu_to_be32(x) + +#if (LINUX_VERSION_CODE < 0x020327) +#define __raw_readl readl +#define __raw_writel writel +#endif + +#define MM_MEMWRITEL(ptr, val) __raw_writel(val, ptr) +#define MM_MEMREADL(ptr) __raw_readl(ptr) + +typedef atomic_t MM_ATOMIC_T; + +#define MM_ATOMIC_SET(ptr, val) atomic_set(ptr, val) +#define MM_ATOMIC_READ(ptr) atomic_read(ptr) +#define MM_ATOMIC_INC(ptr) atomic_inc(ptr) +#define MM_ATOMIC_ADD(ptr, val) atomic_add(val, ptr) +#define MM_ATOMIC_DEC(ptr) atomic_dec(ptr) +#define MM_ATOMIC_SUB(ptr, val) atomic_sub(val, ptr) + +#define MM_MB() mb() +#define MM_WMB() wmb() +#define MM_RMB() rmb() + +#include "lm.h" +#include "queue.h" +#include "tigon3.h" + +#if DBG +#define STATIC +#else +#define STATIC static +#endif + +extern int MM_Packet_Desc_Size; + +#define MM_PACKET_DESC_SIZE MM_Packet_Desc_Size + +DECLARE_QUEUE_TYPE(UM_RX_PACKET_Q, MAX_RX_PACKET_DESC_COUNT+1); + +#define MAX_MEM 16 +#define MAX_MEM2 4 + +#if (LINUX_VERSION_CODE < 0x020211) +typedef u32 dma_addr_t; +#endif + +#if (LINUX_VERSION_CODE < 0x02032a) +#define pci_map_single(dev, address, size, dir) virt_to_bus(address) +#define pci_unmap_single(dev, dma_addr, size, dir) +#endif + +#if MAX_SKB_FRAGS +#if (LINUX_VERSION_CODE >= 0x02040d) + +typedef dma_addr_t dmaaddr_high_t; + +#else + +#if defined(CONFIG_HIGHMEM) && defined(CONFIG_X86) && ! defined(CONFIG_X86_64) + +#if defined(CONFIG_HIGHMEM64G) +typedef unsigned long long dmaaddr_high_t; +#else +typedef dma_addr_t dmaaddr_high_t; +#endif + +#ifndef pci_map_page +#define pci_map_page bcm_pci_map_page +#endif + +static inline dmaaddr_high_t +bcm_pci_map_page(struct pci_dev *dev, struct page *page, + int offset, size_t size, int dir) +{ + dmaaddr_high_t phys; + + phys = (page-mem_map) * (dmaaddr_high_t) PAGE_SIZE + offset; + + return phys; +} + +#ifndef pci_unmap_page +#define pci_unmap_page(dev, map, size, dir) +#endif + +#else /* #if defined(CONFIG_HIGHMEM) && defined(CONFIG_X86) && ! defined(CONFIG_X86_64)*/ + +typedef dma_addr_t dmaaddr_high_t; + +/* Warning - This may not work for all architectures if HIGHMEM is defined */ + +#ifndef pci_map_page +#define pci_map_page(dev, page, offset, size, dir) \ + pci_map_single(dev, page_address(page) + (offset), size, dir) +#endif +#ifndef pci_unmap_page +#define pci_unmap_page(dev, map, size, dir) \ + pci_unmap_single(dev, map, size, dir) +#endif + +#endif /* #if defined(CONFIG_HIGHMEM) && defined(CONFIG_X86) && ! defined(CONFIG_X86_64)*/ + +#endif /* #if (LINUX_VERSION_CODE >= 0x02040d)*/ +#endif /* #if MAX_SKB_FRAGS*/ + +#if defined (CONFIG_X86) && ! defined(CONFIG_X86_64) +#define NO_PCI_UNMAP 1 +#endif + +#if (LINUX_VERSION_CODE < 0x020412) +#if ! defined (NO_PCI_UNMAP) +#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) dma_addr_t ADDR_NAME; +#define DECLARE_PCI_UNMAP_LEN(LEN_NAME) __u32 LEN_NAME; + +#define pci_unmap_addr(PTR, ADDR_NAME) \ + ((PTR)->ADDR_NAME) + +#define pci_unmap_len(PTR, LEN_NAME) \ + ((PTR)->LEN_NAME) + +#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) \ + (((PTR)->ADDR_NAME) = (VAL)) + +#define pci_unmap_len_set(PTR, LEN_NAME, VAL) \ + (((PTR)->LEN_NAME) = (VAL)) +#else +#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) +#define DECLARE_PCI_UNMAP_LEN(ADDR_NAME) + +#define pci_unmap_addr(PTR, ADDR_NAME) 0 +#define pci_unmap_len(PTR, LEN_NAME) 0 +#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0) +#define pci_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0) +#endif +#endif + +#if (LINUX_VERSION_CODE < 0x02030e) +#define net_device device +#define netif_carrier_on(dev) +#define netif_carrier_off(dev) +#endif + +#if (LINUX_VERSION_CODE < 0x02032b) +#define tasklet_struct tq_struct +#endif + +typedef struct _UM_DEVICE_BLOCK { + LM_DEVICE_BLOCK lm_dev; + struct net_device *dev; + struct pci_dev *pdev; + struct net_device *next_module; + char *name; +#ifdef BCM_PROC_FS + struct proc_dir_entry *pfs_entry; + char pfs_name[32]; +#endif + void *mem_list[MAX_MEM]; + dma_addr_t dma_list[MAX_MEM]; + int mem_size_list[MAX_MEM]; + int mem_list_num; + +#ifdef NICE_SUPPORT + void *mem_list2[MAX_MEM2]; /* for diagnostics ioctl */ + dma_addr_t dma_list2[MAX_MEM2]; + __u64 cpu_pa_list2[MAX_MEM2]; + int mem_size_list2[MAX_MEM2]; +#endif + int index; + int opened; + int suspended; + int using_dac; /* dual address cycle */ + int delayed_link_ind; /* Delay link status during initial load */ + int adapter_just_inited; /* the first few seconds after init. */ + int timer_interval; + int adaptive_expiry; + int crc_counter_expiry; + int poll_tbi_interval; + int poll_tbi_expiry; + int asf_heartbeat; + int stats_interval; + int tx_full; + int tx_queued; + int line_speed; /* in Mbps, 0 if link is down */ + UM_RX_PACKET_Q rx_out_of_buf_q; + int rx_out_of_buf; + int rx_buf_repl_thresh; + int rx_buf_repl_panic_thresh; + int rx_buf_repl_isr_limit; + int rx_buf_align; + struct timer_list timer; + int do_global_lock; + spinlock_t global_lock; + spinlock_t undi_lock; + spinlock_t phy_lock; + unsigned long undi_flags; + volatile unsigned long interrupt; + atomic_t intr_sem; + int tasklet_pending; + volatile unsigned long tasklet_busy; + struct tasklet_struct tasklet; + struct net_device_stats stats; +#ifdef NICE_SUPPORT + void (*nice_rx)( struct sk_buff*, void* ); + void* nice_ctx; +#endif /* NICE_SUPPORT */ + int intr_test; + int intr_test_result; +#ifdef NETIF_F_HW_VLAN_TX + struct vlan_group *vlgrp; +#endif + int vlan_tag_mode; /* Setting to allow ASF to work properly with */ + /* VLANs */ + #define VLAN_TAG_MODE_AUTO_STRIP 0 + #define VLAN_TAG_MODE_NORMAL_STRIP 1 + #define VLAN_TAG_MODE_FORCED_STRIP 2 + + /* Auto mode - VLAN TAGs are always stripped if ASF is enabled, */ + /* If ASF is not enabled, it will be in normal mode. */ + /* Normal mode - VLAN TAGs are stripped when VLANs are registered */ + /* Forced mode - VLAN TAGs are always stripped. */ + + int adaptive_coalesce; + uint rx_last_cnt; + uint tx_last_cnt; + uint rx_curr_coalesce_frames; + uint rx_curr_coalesce_frames_intr; + uint rx_curr_coalesce_ticks; + uint tx_curr_coalesce_frames; +#if TIGON3_DEBUG + unsigned long tx_zc_count; + unsigned long tx_chksum_count; + unsigned long tx_himem_count; + unsigned long rx_good_chksum_count; +#endif + unsigned long rx_bad_chksum_count; +#ifdef BCM_TSO + unsigned long tso_pkt_count; +#endif + unsigned long rx_misc_errors; + uint64_t phy_crc_count; + unsigned int spurious_int; +} UM_DEVICE_BLOCK, *PUM_DEVICE_BLOCK; + +typedef struct _UM_PACKET { + LM_PACKET lm_packet; + struct sk_buff *skbuff; +#if MAX_SKB_FRAGS + DECLARE_PCI_UNMAP_ADDR(map[MAX_SKB_FRAGS + 1]) + DECLARE_PCI_UNMAP_LEN(map_len[MAX_SKB_FRAGS + 1]) +#else + DECLARE_PCI_UNMAP_ADDR(map[1]) + DECLARE_PCI_UNMAP_LEN(map_len[1]) +#endif +} UM_PACKET, *PUM_PACKET; + +static inline void MM_SetAddr(LM_PHYSICAL_ADDRESS *paddr, dma_addr_t addr) +{ +#if (BITS_PER_LONG == 64) + paddr->High = ((unsigned long) addr) >> 32; + paddr->Low = ((unsigned long) addr) & 0xffffffff; +#else + paddr->High = 0; + paddr->Low = (unsigned long) addr; +#endif +} + +static inline void MM_SetT3Addr(T3_64BIT_HOST_ADDR *paddr, dma_addr_t addr) +{ +#if (BITS_PER_LONG == 64) + paddr->High = ((unsigned long) addr) >> 32; + paddr->Low = ((unsigned long) addr) & 0xffffffff; +#else + paddr->High = 0; + paddr->Low = (unsigned long) addr; +#endif +} + +#if MAX_SKB_FRAGS +static inline void MM_SetT3AddrHigh(T3_64BIT_HOST_ADDR *paddr, + dmaaddr_high_t addr) +{ +#if defined(CONFIG_HIGHMEM64G) && defined(CONFIG_X86) && ! defined(CONFIG_X86_64) + paddr->High = (unsigned long) (addr >> 32); + paddr->Low = (unsigned long) (addr & 0xffffffff); +#else + MM_SetT3Addr(paddr, (dma_addr_t) addr); +#endif +} +#endif + +static inline void MM_MapRxDma(PLM_DEVICE_BLOCK pDevice, + struct _LM_PACKET *pPacket, + T3_64BIT_HOST_ADDR *paddr) +{ + dma_addr_t map; + struct sk_buff *skb = ((struct _UM_PACKET *) pPacket)->skbuff; + + map = pci_map_single(((struct _UM_DEVICE_BLOCK *)pDevice)->pdev, + skb->tail, + pPacket->u.Rx.RxBufferSize, + PCI_DMA_FROMDEVICE); + pci_unmap_addr_set(((struct _UM_PACKET *) pPacket), map[0], map); + MM_SetT3Addr(paddr, map); +} + +static inline void MM_MapTxDma(PLM_DEVICE_BLOCK pDevice, + struct _LM_PACKET *pPacket, + T3_64BIT_HOST_ADDR *paddr, + LM_UINT32 *len, + int frag) +{ + dma_addr_t map; + struct sk_buff *skb = ((struct _UM_PACKET *) pPacket)->skbuff; + unsigned int length; + + if (frag == 0) { +#if MAX_SKB_FRAGS + if (skb_shinfo(skb)->nr_frags) + length = skb->len - skb->data_len; + else +#endif + length = skb->len; + map = pci_map_single(((struct _UM_DEVICE_BLOCK *)pDevice)->pdev, + skb->data, length, PCI_DMA_TODEVICE); + MM_SetT3Addr(paddr, map); + pci_unmap_addr_set(((struct _UM_PACKET *)pPacket), map[0], map); + pci_unmap_len_set(((struct _UM_PACKET *) pPacket), map_len[0], + length); + *len = length; + } +#if MAX_SKB_FRAGS + else { + skb_frag_t *sk_frag; + dmaaddr_high_t hi_map; + + sk_frag = &skb_shinfo(skb)->frags[frag - 1]; + + hi_map = pci_map_page( + ((struct _UM_DEVICE_BLOCK *)pDevice)->pdev, + sk_frag->page, + sk_frag->page_offset, + sk_frag->size, PCI_DMA_TODEVICE); + + MM_SetT3AddrHigh(paddr, hi_map); + pci_unmap_addr_set(((struct _UM_PACKET *) pPacket), map[frag], + hi_map); + pci_unmap_len_set(((struct _UM_PACKET *) pPacket), + map_len[frag], sk_frag->size); + *len = sk_frag->size; + } +#endif +} + +#define BCM5700_PHY_LOCK(pUmDevice, flags) { \ + spinlock_t *lock; \ + if ((pUmDevice)->do_global_lock) { \ + lock = &(pUmDevice)->global_lock; \ + } \ + else { \ + lock = &(pUmDevice)->phy_lock; \ + } \ + spin_lock_irqsave(lock, flags); \ +} + +#define BCM5700_PHY_UNLOCK(pUmDevice, flags) { \ + spinlock_t *lock; \ + if ((pUmDevice)->do_global_lock) { \ + lock = &(pUmDevice)->global_lock; \ + } \ + else { \ + lock = &(pUmDevice)->phy_lock; \ + } \ + spin_unlock_irqrestore(lock, flags); \ +} + + +#define MM_ACQUIRE_UNDI_LOCK(_pDevice) \ + if (!(((PUM_DEVICE_BLOCK)(_pDevice))->do_global_lock)) { \ + unsigned long flags; \ + spin_lock_irqsave(&((PUM_DEVICE_BLOCK)(_pDevice))->undi_lock, flags); \ + ((PUM_DEVICE_BLOCK)(_pDevice))->undi_flags = flags; \ + } + +#define MM_RELEASE_UNDI_LOCK(_pDevice) \ + if (!(((PUM_DEVICE_BLOCK)(_pDevice))->do_global_lock)) { \ + unsigned long flags = ((PUM_DEVICE_BLOCK) (_pDevice))->undi_flags; \ + spin_unlock_irqrestore(&((PUM_DEVICE_BLOCK)(_pDevice))->undi_lock, flags); \ + } + +#define MM_ACQUIRE_PHY_LOCK_IN_IRQ(_pDevice) \ + if (!(((PUM_DEVICE_BLOCK)(_pDevice))->do_global_lock)) { \ + spin_lock(&((PUM_DEVICE_BLOCK)(_pDevice))->phy_lock); \ + } + +#define MM_RELEASE_PHY_LOCK_IN_IRQ(_pDevice) \ + if (!(((PUM_DEVICE_BLOCK)(_pDevice))->do_global_lock)) { \ + spin_unlock(&((PUM_DEVICE_BLOCK)(_pDevice))->phy_lock); \ + } + +#define MM_UINT_PTR(_ptr) ((unsigned long) (_ptr)) + +#define MM_GETSTATS64(_Ctr) \ + (uint64_t) (_Ctr).Low + ((uint64_t) (_Ctr).High << 32) + +#define MM_GETSTATS32(_Ctr) \ + (uint32_t) (_Ctr).Low + +#if (BITS_PER_LONG == 64) +#define MM_GETSTATS(_Ctr) (unsigned long) MM_GETSTATS64(_Ctr) +#else +#define MM_GETSTATS(_Ctr) (unsigned long) MM_GETSTATS32(_Ctr) +#endif + + +#define printf(fmt, args...) printk(KERN_WARNING fmt, ##args) + +#define DbgPrint(fmt, arg...) printk(KERN_DEBUG fmt, ##arg) +#if defined(CONFIG_X86) +#define DbgBreakPoint() __asm__("int $129") +#else +#define DbgBreakPoint() +#endif +#define MM_Wait(time) udelay(time) + +#endif diff -u --recursive --new-file linux-2.4.26/drivers/net/bcm/nicext.h linux-2.4.26.patch/drivers/net/bcm/nicext.h --- linux-2.4.26/drivers/net/bcm/nicext.h 1969-12-31 16:00:00.000000000 -0800 +++ linux-2.4.26.patch/drivers/net/bcm/nicext.h 2004-06-22 16:07:37.000000000 -0700 @@ -0,0 +1,214 @@ +/**************************************************************************** + * Copyright(c) 2000-2003 Broadcom Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation. + * + * Name: nicext.h + * + * Description: Broadcom Network Interface Card Extension (NICE) is an + * extension to Linux NET device kernel mode drivers. + * NICE is designed to provide additional functionalities, + * such as receive packet intercept. To support Broadcom NICE, + * the network device driver can be modified by adding an + * device ioctl handler and by indicating receiving packets + * to the NICE receive handler. Broadcom NICE will only be + * enabled by a NICE-aware intermediate driver, such as + * Broadcom Advanced Server Program Driver (BASP). When NICE + * is not enabled, the modified network device drivers + * functions exactly as other non-NICE aware drivers. + * + * Author: Frankie Fan + * + * Created: September 17, 2000 + * + ****************************************************************************/ +#ifndef _nicext_h_ +#define _nicext_h_ + +/* + * ioctl for NICE + */ +#define SIOCNICE SIOCDEVPRIVATE+7 + +/* + * SIOCNICE: + * + * The following structure needs to be less than IFNAMSIZ (16 bytes) because + * we're overloading ifreq.ifr_ifru. + * + * If 16 bytes is not enough, we should consider relaxing this because + * this is no field after ifr_ifru in the ifreq structure. But we may + * run into future compatiability problem in case of changing struct ifreq. + */ +struct nice_req +{ + __u32 cmd; + + union + { +#ifdef __KERNEL__ + /* cmd = NICE_CMD_SET_RX or NICE_CMD_GET_RX */ + /* cmd = NICE_CMD_SET_RX_NAPI or NICE_CMD_GET_RX_NAPI */ + struct + { + void (*nrqus1_rx)( struct sk_buff*, void* ); + void* nrqus1_ctx; + } nrqu_nrqus1; + + /* cmd = NICE_CMD_QUERY_SUPPORT */ + struct + { + __u32 nrqus2_magic; + __u32 nrqus2_support_rx:1; + __u32 nrqus2_support_vlan:1; + __u32 nrqus2_support_get_speed:1; + __u32 nrqus2_support_rx_napi:1; + } nrqu_nrqus2; +#endif + + void *align_ptr; /* this field is not used, it is to align the union */ + /* in 64-bit user mode */ + + /* cmd = NICE_CMD_GET_SPEED - in Mbps or 0 if link down */ + /* cmd = NICE_CMD_ENABLE_EXT_LOOPBACK - in Mbps */ + struct + { + unsigned int nrqus3_speed; /* 1000 = Gb, 100 = 100mbs, 10 = 10mbs */ + } nrqu_nrqus3; + + /* cmd = NICE_CMD_BLINK_LED */ + struct + { + unsigned int nrqus4_blink_time; /* blink duration in seconds */ + } nrqu_nrqus4; + + /* cmd = NICE_CMD_REG_READ */ + /* cmd = NICE_CMD_REG_WRITE */ + /* cmd = NICE_CMD_MEM_READ */ + /* cmd = NICE_CMD_MEM_WRITE */ + /* cmd = NICE_CMD_REG_READ_DIRECT */ + /* cmd = NICE_CMD_REG_WRITE_DIRECT */ + /* cmd = NICE_CMD_CFG_READ32 */ + /* cmd = NICE_CMD_CFG_READ16 */ + /* cmd = NICE_CMD_CFG_READ8 */ + /* cmd = NICE_CMD_CFG_WRITE32 */ + /* cmd = NICE_CMD_CFG_WRITE16 */ + /* cmd = NICE_CMD_CFG_WRITE8 */ + struct + { + unsigned int nrqus5_offset; /* offset */ + unsigned int nrqus5_data; /* value */ + } nrqu_nrqus5; + + /* cmd = NICE_CMD_INTERRUPT_TEST */ + struct + { + unsigned int nrqus6_intr_test_result; /* 1 == pass */ + } nrqu_nrqus6; + + /* cmd = NICE_CMD_KMALLOC_PHYS */ + /* cmd = NICE_CMD_KFREE_PHYS */ + /* These commands allow the diagnostics app. to allocate and free */ + /* PCI consistent memory for DMA tests */ + struct + { + unsigned int nrqus7_size; /* size(bytes) to allocate, not used */ + /* when cmd is NICE_CMD_KFREE_PHYS. */ + __u32 nrqus7_phys_addr_lo;/* CPU physical address allocated or */ + __u32 nrqus7_phys_addr_hi;/* to be freed. */ + /* PCI physical address is contained in */ + /* the 1st 64 bit of the allocated */ + /* buffer. Use open("/dev/mem")/lseek() */ + /* and read()/write() to a access */ + /* buffer in user space. */ + /* mmap() only works on x86. */ + } nrqu_nrqus7; + + /* cmd = NICE_CMD_SET_WRITE_PROTECT */ + struct + { + unsigned int nrqus8_data; /* 1 == set write protect, 0 == clear write protect */ + } nrqu_nrqus8; + + /* cmd = NICE_CMD_GET_STATS_BLOCK */ + struct + { + void *nrqus9_useraddr; /* user space address for the stats block */ + unsigned int nrqus9_size;/* size (in bytes) */ + /* (0x6c0 for the whole block) */ + } nrqu_nrqus9; + + } nrq_nrqu; +}; + +#define nrq_rx nrq_nrqu.nrqu_nrqus1.nrqus1_rx +#define nrq_ctx nrq_nrqu.nrqu_nrqus1.nrqus1_ctx +#define nrq_support_rx nrq_nrqu.nrqu_nrqus2.nrqus2_support_rx +#define nrq_magic nrq_nrqu.nrqu_nrqus2.nrqus2_magic +#define nrq_support_vlan nrq_nrqu.nrqu_nrqus2.nrqus2_support_vlan +#define nrq_support_get_speed nrq_nrqu.nrqu_nrqus2.nrqus2_support_get_speed +#define nrq_support_rx_napi nrq_nrqu.nrqu_nrqus2.nrqus2_support_rx_napi +#define nrq_speed nrq_nrqu.nrqu_nrqus3.nrqus3_speed +#define nrq_blink_time nrq_nrqu.nrqu_nrqus4.nrqus4_blink_time +#define nrq_offset nrq_nrqu.nrqu_nrqus5.nrqus5_offset +#define nrq_data nrq_nrqu.nrqu_nrqus5.nrqus5_data +#define nrq_intr_test_result nrq_nrqu.nrqu_nrqus6.nrqus6_intr_test_result +#define nrq_size nrq_nrqu.nrqu_nrqus7.nrqus7_size +#define nrq_phys_addr_lo nrq_nrqu.nrqu_nrqus7.nrqus7_phys_addr_lo +#define nrq_phys_addr_hi nrq_nrqu.nrqu_nrqus7.nrqus7_phys_addr_hi +#define nrq_write_protect nrq_nrqu.nrqu_nrqus8.nrqus8_data +#define nrq_stats_useraddr nrq_nrqu.nrqu_nrqus9.nrqus9_useraddr +#define nrq_stats_size nrq_nrqu.nrqu_nrqus9.nrqus9_size + +/* + * magic constants + */ +#define NICE_REQUESTOR_MAGIC 0x4543494E // NICE in ascii +#define NICE_DEVICE_MAGIC 0x4E494345 // ECIN in ascii + +/* + * command field + */ +typedef enum { + NICE_CMD_QUERY_SUPPORT = 0x00000001, + NICE_CMD_SET_RX = 0x00000002, + NICE_CMD_GET_RX = 0x00000003, + NICE_CMD_GET_SPEED = 0x00000004, + NICE_CMD_BLINK_LED = 0x00000005, + NICE_CMD_DIAG_SUSPEND = 0x00000006, + NICE_CMD_DIAG_RESUME = 0x00000007, + NICE_CMD_REG_READ = 0x00000008, + NICE_CMD_REG_WRITE = 0x00000009, + NICE_CMD_MEM_READ = 0x0000000a, + NICE_CMD_MEM_WRITE = 0x0000000b, + NICE_CMD_ENABLE_MAC_LOOPBACK = 0x0000000c, + NICE_CMD_DISABLE_MAC_LOOPBACK = 0x0000000d, + NICE_CMD_ENABLE_PHY_LOOPBACK = 0x0000000e, + NICE_CMD_DISABLE_PHY_LOOPBACK = 0x0000000f, + NICE_CMD_INTERRUPT_TEST = 0x00000010, + NICE_CMD_SET_WRITE_PROTECT = 0x00000011, + NICE_CMD_SET_RX_NAPI = 0x00000012, + NICE_CMD_GET_RX_NAPI = 0x00000013, + NICE_CMD_ENABLE_EXT_LOOPBACK = 0x00000014, + NICE_CMD_DISABLE_EXT_LOOPBACK = 0x00000015, + NICE_CMD_CFG_READ32 = 0x00000016, + NICE_CMD_CFG_READ16 = 0x00000017, + NICE_CMD_CFG_READ8 = 0x00000018, + NICE_CMD_CFG_WRITE32 = 0x00000019, + NICE_CMD_CFG_WRITE16 = 0x0000001a, + NICE_CMD_CFG_WRITE8 = 0x0000001b, + + NICE_CMD_REG_READ_DIRECT = 0x0000001e, + NICE_CMD_REG_WRITE_DIRECT = 0x0000001f, + NICE_CMD_RESET = 0x00000020, + NICE_CMD_KMALLOC_PHYS = 0x00000021, + NICE_CMD_KFREE_PHYS = 0x00000022, + NICE_CMD_GET_STATS_BLOCK = 0x00000023, + NICE_CMD_CLR_STATS_BLOCK = 0x00000024, + NICE_CMD_MAX +} nice_cmds; + +#endif // _nicext_h_ + diff -u --recursive --new-file linux-2.4.26/drivers/net/bcm/queue.h linux-2.4.26.patch/drivers/net/bcm/queue.h --- linux-2.4.26/drivers/net/bcm/queue.h 1969-12-31 16:00:00.000000000 -0800 +++ linux-2.4.26.patch/drivers/net/bcm/queue.h 2004-06-22 16:07:37.000000000 -0700 @@ -0,0 +1,347 @@ +/******************************************************************************/ +/* */ +/* Broadcom BCM5700 Linux Network Driver, Copyright (c) 2000 - 2003 Broadcom */ +/* Corporation. */ +/* All rights reserved. */ +/* */ +/* This program is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU General Public License as published by */ +/* the Free Software Foundation, located in the file LICENSE. */ +/* */ +/* Queue functions. */ +/* void QQ_InitQueue(PQQ_CONTAINER pQueue) */ +/* char QQ_Full(PQQ_CONTAINER pQueue) */ +/* char QQ_Empty(PQQ_CONTAINER pQueue) */ +/* unsigned int QQ_GetSize(PQQ_CONTAINER pQueue) */ +/* unsigned int QQ_GetEntryCnt(PQQ_CONTAINER pQueue) */ +/* char QQ_PushHead(PQQ_CONTAINER pQueue, PQQ_ENTRY pEntry) */ +/* char QQ_PushTail(PQQ_CONTAINER pQueue, PQQ_ENTRY pEntry) */ +/* PQQ_ENTRY QQ_PopHead(PQQ_CONTAINER pQueue) */ +/* PQQ_ENTRY QQ_PopTail(PQQ_CONTAINER pQueue) */ +/* PQQ_ENTRY QQ_GetHead(PQQ_CONTAINER pQueue, unsigned int Idx) */ +/* PQQ_ENTRY QQ_GetTail(PQQ_CONTAINER pQueue, unsigned int Idx) */ +/* */ +/* */ +/* History: */ +/* 02/25/00 Hav Khauv Initial version. */ +/******************************************************************************/ + +#ifndef BCM_QUEUE_H +#define BCM_QUEUE_H + + + +/******************************************************************************/ +/* Queue definitions. */ +/******************************************************************************/ + +/* Entry for queueing. */ +typedef void *PQQ_ENTRY; + + +/* Queue header -- base type. */ +typedef struct { + unsigned int Head; + unsigned int Tail; + unsigned int Size; + MM_ATOMIC_T EntryCnt; + PQQ_ENTRY Array[1]; +} QQ_CONTAINER, *PQQ_CONTAINER; + + +/* Declare queue type macro. */ +#define DECLARE_QUEUE_TYPE(_QUEUE_TYPE, _QUEUE_SIZE) \ + \ + typedef struct { \ + QQ_CONTAINER Container; \ + PQQ_ENTRY EntryBuffer[_QUEUE_SIZE]; \ + } _QUEUE_TYPE, *P##_QUEUE_TYPE + + + +/******************************************************************************/ +/* Compilation switches. */ +/******************************************************************************/ + +#if DBG +#undef QQ_NO_OVERFLOW_CHECK +#undef QQ_NO_UNDERFLOW_CHECK +#endif /* DBG */ + +#ifdef QQ_USE_MACROS +/* notdone */ +#else + +#ifdef QQ_NO_INLINE +#define __inline +#endif /* QQ_NO_INLINE */ + + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +__inline static void +QQ_InitQueue( +PQQ_CONTAINER pQueue, +unsigned int QueueSize) { + pQueue->Head = 0; + pQueue->Tail = 0; + pQueue->Size = QueueSize+1; + MM_ATOMIC_SET(&pQueue->EntryCnt, 0); +} /* QQ_InitQueue */ + + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +__inline static char +QQ_Full( +PQQ_CONTAINER pQueue) { + unsigned int NewHead; + + NewHead = (pQueue->Head + 1) % pQueue->Size; + + return(NewHead == pQueue->Tail); +} /* QQ_Full */ + + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +__inline static char +QQ_Empty( +PQQ_CONTAINER pQueue) { + return(pQueue->Head == pQueue->Tail); +} /* QQ_Empty */ + + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +__inline static unsigned int +QQ_GetSize( +PQQ_CONTAINER pQueue) { + return pQueue->Size; +} /* QQ_GetSize */ + + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +__inline static unsigned int +QQ_GetEntryCnt( +PQQ_CONTAINER pQueue) { + return MM_ATOMIC_READ(&pQueue->EntryCnt); +} /* QQ_GetEntryCnt */ + + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/* TRUE entry was added successfully. */ +/* FALSE queue is full. */ +/******************************************************************************/ +__inline static char +QQ_PushHead( +PQQ_CONTAINER pQueue, +PQQ_ENTRY pEntry) { + unsigned int Head; + + Head = (pQueue->Head + 1) % pQueue->Size; + +#if !defined(QQ_NO_OVERFLOW_CHECK) + if(Head == pQueue->Tail) { + return 0; + } /* if */ +#endif /* QQ_NO_OVERFLOW_CHECK */ + + pQueue->Array[pQueue->Head] = pEntry; + MM_WMB(); + pQueue->Head = Head; + MM_ATOMIC_INC(&pQueue->EntryCnt); + + return -1; +} /* QQ_PushHead */ + + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/* TRUE entry was added successfully. */ +/* FALSE queue is full. */ +/******************************************************************************/ +__inline static char +QQ_PushTail( +PQQ_CONTAINER pQueue, +PQQ_ENTRY pEntry) { + unsigned int Tail; + + Tail = pQueue->Tail; + if(Tail == 0) { + Tail = pQueue->Size; + } /* if */ + Tail--; + +#if !defined(QQ_NO_OVERFLOW_CHECK) + if(Tail == pQueue->Head) { + return 0; + } /* if */ +#endif /* QQ_NO_OVERFLOW_CHECK */ + + pQueue->Array[Tail] = pEntry; + MM_WMB(); + pQueue->Tail = Tail; + MM_ATOMIC_INC(&pQueue->EntryCnt); + + return -1; +} /* QQ_PushTail */ + + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +__inline static PQQ_ENTRY +QQ_PopHead( +PQQ_CONTAINER pQueue) { + unsigned int Head; + unsigned int Tail; + PQQ_ENTRY Entry; + + Head = pQueue->Head; + Tail = pQueue->Tail; + + MM_MB(); +#if !defined(QQ_NO_UNDERFLOW_CHECK) + if(Head == Tail) { + return (PQQ_ENTRY) 0; + } /* if */ +#endif /* QQ_NO_UNDERFLOW_CHECK */ + + if(Head == 0) { + Head = pQueue->Size; + } /* if */ + Head--; + + Entry = pQueue->Array[Head]; + MM_MB(); + pQueue->Head = Head; + MM_ATOMIC_DEC(&pQueue->EntryCnt); + + return Entry; +} /* QQ_PopHead */ + + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +__inline static PQQ_ENTRY +QQ_PopTail( +PQQ_CONTAINER pQueue) { + unsigned int Head; + unsigned int Tail; + PQQ_ENTRY Entry; + + Head = pQueue->Head; + Tail = pQueue->Tail; + + MM_MB(); +#if !defined(QQ_NO_UNDERFLOW_CHECK) + if(Tail == Head) { + return (PQQ_ENTRY) 0; + } /* if */ +#endif /* QQ_NO_UNDERFLOW_CHECK */ + + Entry = pQueue->Array[Tail]; + MM_MB(); + pQueue->Tail = (Tail + 1) % pQueue->Size; + MM_ATOMIC_DEC(&pQueue->EntryCnt); + + return Entry; +} /* QQ_PopTail */ + + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +__inline static PQQ_ENTRY +QQ_GetHead( + PQQ_CONTAINER pQueue, + unsigned int Idx) +{ + if(Idx >= (unsigned int) MM_ATOMIC_READ(&pQueue->EntryCnt)) + { + return (PQQ_ENTRY) 0; + } + + if(pQueue->Head > Idx) + { + Idx = pQueue->Head - Idx; + } + else + { + Idx = pQueue->Size - (Idx - pQueue->Head); + } + Idx--; + + return pQueue->Array[Idx]; +} + + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +__inline static PQQ_ENTRY +QQ_GetTail( + PQQ_CONTAINER pQueue, + unsigned int Idx) +{ + if(Idx >= (unsigned int) MM_ATOMIC_READ(&pQueue->EntryCnt)) + { + return (PQQ_ENTRY) 0; + } + + Idx += pQueue->Tail; + if(Idx >= pQueue->Size) + { + Idx = Idx - pQueue->Size; + } + + return pQueue->Array[Idx]; +} + +#endif /* QQ_USE_MACROS */ + + + +#endif /* QUEUE_H */ diff -u --recursive --new-file linux-2.4.26/drivers/net/bcm/tcp_seg.c linux-2.4.26.patch/drivers/net/bcm/tcp_seg.c --- linux-2.4.26/drivers/net/bcm/tcp_seg.c 1969-12-31 16:00:00.000000000 -0800 +++ linux-2.4.26.patch/drivers/net/bcm/tcp_seg.c 2004-06-22 16:07:37.000000000 -0700 @@ -0,0 +1,106 @@ +/******************************************************************************/ +/* */ +/* Broadcom BCM5700 Linux Network Driver, Copyright (c) 2002 - 2003 Broadcom */ +/* Corporation. */ +/* All rights reserved. */ +/* */ +/* This program is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU General Public License as published by */ +/* the Free Software Foundation, located in the file LICENSE. */ +/* */ +/* History: */ +/* */ +/******************************************************************************/ + +#include "mm.h" + +#if INCLUDE_TCP_SEG_SUPPORT +#include "fw_stkoffld.h" +#include "fw_lso05.h" + +LM_UINT32 LM_GetStkOffLdFirmwareSize(PLM_DEVICE_BLOCK pDevice) +{ + LM_UINT32 FwSize; + + if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5750) + { + return 0; + } + if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5705) + { + FwSize = (LM_UINT32)(t3StkOffLd05FwTextLen + + t3StkOffLd05FwRodataLen + + t3StkOffLd05FwDataLen + + t3StkOffLd05FwSbssLen + + t3StkOffLd05FwBssLen); + } + else + { + FwSize = (LM_UINT32)(t3StkOffLdFwTextLen + + t3StkOffLdFwRodataLen + + t3StkOffLdFwDataLen + + t3StkOffLdFwSbssLen + + t3StkOffLdFwBssLen); + } + + return FwSize; +} + +LM_STATUS LM_LoadStkOffLdFirmware(PLM_DEVICE_BLOCK pDevice) +{ + T3_FWIMG_INFO FwImgInfo; + LM_UINT32 Cpu; + + if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5750) + { + return LM_STATUS_SUCCESS; + } + if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5705) + { + FwImgInfo.StartAddress = t3StkOffLd05FwStartAddr; + FwImgInfo.Text.Buffer = (PLM_UINT8)t3StkOffLd05FwText; + FwImgInfo.Text.Offset = t3StkOffLd05FwTextAddr; + FwImgInfo.Text.Length = t3StkOffLd05FwTextLen; + FwImgInfo.ROnlyData.Buffer = (PLM_UINT8)t3StkOffLd05FwRodata; + FwImgInfo.ROnlyData.Offset = t3StkOffLd05FwRodataAddr; + FwImgInfo.ROnlyData.Length = t3StkOffLd05FwRodataLen; + FwImgInfo.Data.Buffer = (PLM_UINT8)t3StkOffLd05FwData; + FwImgInfo.Data.Offset = t3StkOffLd05FwDataAddr; + FwImgInfo.Data.Length = t3StkOffLd05FwDataLen; + FwImgInfo.Sbss.Offset = t3StkOffLd05FwSbssAddr; + FwImgInfo.Sbss.Length = t3StkOffLd05FwSbssLen; + FwImgInfo.Bss.Offset = t3StkOffLd05FwBssAddr; + FwImgInfo.Bss.Length = t3StkOffLd05FwBssLen; + Cpu = T3_RX_CPU_ID; + } + else + { + FwImgInfo.StartAddress = t3StkOffLdFwStartAddr; + FwImgInfo.Text.Buffer = (PLM_UINT8)t3StkOffLdFwText; + FwImgInfo.Text.Offset = t3StkOffLdFwTextAddr; + FwImgInfo.Text.Length = t3StkOffLdFwTextLen; + FwImgInfo.ROnlyData.Buffer = (PLM_UINT8)t3StkOffLdFwRodata; + FwImgInfo.ROnlyData.Offset = t3StkOffLdFwRodataAddr; + FwImgInfo.ROnlyData.Length = t3StkOffLdFwRodataLen; + FwImgInfo.Data.Buffer = (PLM_UINT8)t3StkOffLdFwData; + FwImgInfo.Data.Offset = t3StkOffLdFwDataAddr; + FwImgInfo.Data.Length = t3StkOffLdFwDataLen; + FwImgInfo.Sbss.Offset = t3StkOffLdFwSbssAddr; + FwImgInfo.Sbss.Length = t3StkOffLdFwSbssLen; + FwImgInfo.Bss.Offset = t3StkOffLdFwBssAddr; + FwImgInfo.Bss.Length = t3StkOffLdFwBssLen; + Cpu = T3_TX_CPU_ID; + } + + if (LM_LoadFirmware(pDevice, + &FwImgInfo, + Cpu, + Cpu) != LM_STATUS_SUCCESS) + { + return LM_STATUS_FAILURE; + } + + return LM_STATUS_SUCCESS; +} + +#endif /* INCLUDE_TCP_SEG_SUPPORT */ diff -u --recursive --new-file linux-2.4.26/drivers/net/bcm/tigon3.c linux-2.4.26.patch/drivers/net/bcm/tigon3.c --- linux-2.4.26/drivers/net/bcm/tigon3.c 1969-12-31 16:00:00.000000000 -0800 +++ linux-2.4.26.patch/drivers/net/bcm/tigon3.c 2004-06-22 16:07:37.000000000 -0700 @@ -0,0 +1,7905 @@ +/******************************************************************************/ +/* */ +/* Broadcom BCM5700 Linux Network Driver, Copyright (c) 2000 - 2004 Broadcom */ +/* Corporation. */ +/* All rights reserved. */ +/* */ +/* This program is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU General Public License as published by */ +/* the Free Software Foundation, located in the file LICENSE. */ +/* */ +/* History: */ +/******************************************************************************/ + +#include "mm.h" + + + +/******************************************************************************/ +/* Local functions. */ +/******************************************************************************/ + +LM_STATUS LM_Abort(PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_QueueRxPackets(PLM_DEVICE_BLOCK pDevice); + +static LM_STATUS LM_InitBcm540xPhy(PLM_DEVICE_BLOCK pDevice); +static LM_VOID LM_PhyTapPowerMgmt(LM_DEVICE_BLOCK *pDevice); + +LM_VOID LM_ServiceRxInterrupt(PLM_DEVICE_BLOCK pDevice); +LM_VOID LM_ServiceTxInterrupt(PLM_DEVICE_BLOCK pDevice); + +static LM_STATUS LM_ForceAutoNeg(PLM_DEVICE_BLOCK pDevice); +static LM_UINT32 GetPhyAdFlowCntrlSettings(PLM_DEVICE_BLOCK pDevice); +STATIC LM_STATUS LM_SetFlowControl(PLM_DEVICE_BLOCK pDevice, + LM_UINT32 LocalPhyAd, LM_UINT32 RemotePhyAd); +#if INCLUDE_TBI_SUPPORT +STATIC LM_STATUS LM_SetupFiberPhy(PLM_DEVICE_BLOCK pDevice); +STATIC LM_STATUS LM_InitBcm800xPhy(PLM_DEVICE_BLOCK pDevice); +#endif +STATIC LM_STATUS LM_SetupCopperPhy(PLM_DEVICE_BLOCK pDevice); +STATIC LM_VOID LM_SetEthWireSpeed(LM_DEVICE_BLOCK *pDevice); +STATIC LM_STATUS LM_PhyAdvertiseAll(LM_DEVICE_BLOCK *pDevice); +STATIC PLM_ADAPTER_INFO LM_GetAdapterInfoBySsid(LM_UINT16 Svid, LM_UINT16 Ssid); +LM_VOID LM_SwitchVaux(PLM_DEVICE_BLOCK pDevice, PLM_DEVICE_BLOCK pDevice2); +STATIC LM_STATUS LM_DmaTest(PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pBufferVirt, + LM_PHYSICAL_ADDRESS BufferPhy, LM_UINT32 BufferSize); +STATIC LM_STATUS LM_DisableChip(PLM_DEVICE_BLOCK pDevice); +STATIC LM_STATUS LM_ResetChip(PLM_DEVICE_BLOCK pDevice); +STATIC LM_STATUS LM_DisableFW(PLM_DEVICE_BLOCK pDevice); +STATIC LM_STATUS LM_Test4GBoundary(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket, + PT3_SND_BD pSendBd); +STATIC LM_VOID LM_WritePreResetSignatures(LM_DEVICE_BLOCK *pDevice, + LM_RESET_TYPE Mode); +STATIC LM_VOID LM_WritePostResetSignatures(LM_DEVICE_BLOCK *pDevice, + LM_RESET_TYPE Mode); +STATIC LM_VOID LM_WriteLegacySignatures(LM_DEVICE_BLOCK *pDevice, + LM_RESET_TYPE Mode); +STATIC void LM_GetPhyId(LM_DEVICE_BLOCK *pDevice); + +/******************************************************************************/ +/* External functions. */ +/******************************************************************************/ + +LM_STATUS LM_LoadRlsFirmware(PLM_DEVICE_BLOCK pDevice); +#if INCLUDE_TCP_SEG_SUPPORT +LM_STATUS LM_LoadStkOffLdFirmware(PLM_DEVICE_BLOCK pDevice); +LM_UINT32 LM_GetStkOffLdFirmwareSize(PLM_DEVICE_BLOCK pDevice); +#endif + +LM_UINT32 +LM_RegRd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register) +{ +#if PCIX_TARGET_WORKAROUND + if (pDevice->Flags & UNDI_FIX_FLAG) + { + return (LM_RegRdInd(pDevice, Register)); + } + else +#endif + { + return (REG_RD_OFFSET(pDevice, Register)); + } +} + +/* Mainly used to flush posted write before delaying */ +LM_VOID +LM_RegRdBack(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register) +{ + LM_UINT32 dummy; + +#if PCIX_TARGET_WORKAROUND + if (pDevice->Flags & ENABLE_PCIX_FIX_FLAG) + { + return; + } + else +#endif + { + if (pDevice->Flags & REG_RD_BACK_FLAG) + return; + + dummy = REG_RD_OFFSET(pDevice, Register); + } +} + +LM_VOID +LM_RegWr(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register, LM_UINT32 Value32, + LM_UINT32 ReadBack) +{ +#if PCIX_TARGET_WORKAROUND + if (pDevice->Flags & ENABLE_PCIX_FIX_FLAG) + { + LM_RegWrInd(pDevice, Register, Value32); + } + else +#endif + { + LM_UINT32 dummy; + + REG_WR_OFFSET(pDevice, Register, Value32); + if (ReadBack && (pDevice->Flags & REG_RD_BACK_FLAG)) + { + dummy = REG_RD_OFFSET(pDevice, Register); + } + } +} + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +LM_UINT32 +LM_RegRdInd( +PLM_DEVICE_BLOCK pDevice, +LM_UINT32 Register) { + LM_UINT32 Value32; + + MM_ACQUIRE_UNDI_LOCK(pDevice); + MM_WriteConfig32(pDevice, T3_PCI_REG_ADDR_REG, Register); + MM_ReadConfig32(pDevice, T3_PCI_REG_DATA_REG, &Value32); + MM_RELEASE_UNDI_LOCK(pDevice); + + return MM_SWAP_LE32(Value32); +} /* LM_RegRdInd */ + + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +LM_VOID +LM_RegWrInd( +PLM_DEVICE_BLOCK pDevice, +LM_UINT32 Register, +LM_UINT32 Value32) { + + MM_ACQUIRE_UNDI_LOCK(pDevice); + MM_WriteConfig32(pDevice, T3_PCI_REG_ADDR_REG, Register); + MM_WriteConfig32(pDevice, T3_PCI_REG_DATA_REG, MM_SWAP_LE32(Value32)); + MM_RELEASE_UNDI_LOCK(pDevice); +} /* LM_RegWrInd */ + + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +LM_UINT32 +LM_MemRdInd( +PLM_DEVICE_BLOCK pDevice, +LM_UINT32 MemAddr) { + LM_UINT32 Value32; + + MM_ACQUIRE_UNDI_LOCK(pDevice); + MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_ADDR_REG, MemAddr); + MM_ReadConfig32(pDevice, T3_PCI_MEM_WIN_DATA_REG, &Value32); + MM_RELEASE_UNDI_LOCK(pDevice); + + return MM_SWAP_LE32(Value32); +} /* LM_MemRdInd */ + + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +LM_VOID +LM_MemWrInd( +PLM_DEVICE_BLOCK pDevice, +LM_UINT32 MemAddr, +LM_UINT32 Value32) { + MM_ACQUIRE_UNDI_LOCK(pDevice); + MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_ADDR_REG, MemAddr); + MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_DATA_REG, MM_SWAP_LE32(Value32)); + MM_RELEASE_UNDI_LOCK(pDevice); +} /* LM_MemWrInd */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +LM_STATUS +LM_QueueRxPackets( +PLM_DEVICE_BLOCK pDevice) { + LM_STATUS Lmstatus; + PLM_PACKET pPacket; + PT3_RCV_BD pRcvBd = 0; + LM_UINT32 StdBdAdded = 0; +#if T3_JUMBO_RCV_RCB_ENTRY_COUNT + LM_UINT32 JumboBdAdded = 0; +#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ + LM_UINT32 ConIdx, Idx; + LM_UINT32 Diff = 0; + + Lmstatus = LM_STATUS_SUCCESS; + + if (pDevice->Flags & RX_BD_LIMIT_64_FLAG) + { + ConIdx = pDevice->pStatusBlkVirt->RcvStdConIdx; + Diff = (pDevice->RxStdProdIdx - ConIdx) & + T3_STD_RCV_RCB_ENTRY_COUNT_MASK; + if (Diff >= 56) + { + if (QQ_GetEntryCnt(&pDevice->RxPacketFreeQ.Container)) + { + pDevice->QueueAgain = TRUE; + } + return LM_STATUS_SUCCESS; + } + } + + pDevice->QueueAgain = FALSE; + + pPacket = (PLM_PACKET) QQ_PopHead(&pDevice->RxPacketFreeQ.Container); + while(pPacket) { + switch(pPacket->u.Rx.RcvProdRing) { +#if T3_JUMBO_RCV_RCB_ENTRY_COUNT + case T3_JUMBO_RCV_PROD_RING: /* Jumbo Receive Ring. */ + /* Initialize the buffer descriptor. */ + Idx = pDevice->RxJumboProdIdx; + pRcvBd = &pDevice->pRxJumboBdVirt[Idx]; + + pPacket->u.Rx.RcvRingProdIdx = Idx; + pDevice->RxJumboRing[Idx] = pPacket; + /* Update the producer index. */ + pDevice->RxJumboProdIdx = (Idx + 1) & + T3_JUMBO_RCV_RCB_ENTRY_COUNT_MASK; + + JumboBdAdded++; + break; +#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ + + case T3_STD_RCV_PROD_RING: /* Standard Receive Ring. */ + /* Initialize the buffer descriptor. */ + Idx = pDevice->RxStdProdIdx; + pRcvBd = &pDevice->pRxStdBdVirt[Idx]; + + pPacket->u.Rx.RcvRingProdIdx = Idx; + pDevice->RxStdRing[Idx] = pPacket; + /* Update the producer index. */ + pDevice->RxStdProdIdx = (Idx + 1) & + T3_STD_RCV_RCB_ENTRY_COUNT_MASK; + + StdBdAdded++; + break; + + case T3_UNKNOWN_RCV_PROD_RING: + default: + Lmstatus = LM_STATUS_FAILURE; + break; + } /* switch */ + + /* Bail out if there is any error. */ + if(Lmstatus != LM_STATUS_SUCCESS) + { + break; + } + + /* Initialize the receive buffer pointer */ + MM_MapRxDma(pDevice, pPacket, &pRcvBd->HostAddr); + + /* The opaque field may point to an offset from a fix addr. */ + pRcvBd->Opaque = (LM_UINT32) (MM_UINT_PTR(pPacket) - + MM_UINT_PTR(pDevice->pPacketDescBase)); + + if ((pDevice->Flags & RX_BD_LIMIT_64_FLAG) && + ((Diff + StdBdAdded) >= 63)) + { + if (QQ_GetEntryCnt(&pDevice->RxPacketFreeQ.Container)) + { + pDevice->QueueAgain = TRUE; + } + break; + } + pPacket = (PLM_PACKET) QQ_PopHead(&pDevice->RxPacketFreeQ.Container); + } /* while */ + + MM_WMB(); + /* Update the procedure index. */ + if(StdBdAdded) + { + MB_REG_WR(pDevice, Mailbox.RcvStdProdIdx.Low, + pDevice->RxStdProdIdx); + if (pDevice->Flags & FLUSH_POSTED_WRITE_FLAG) + { + MB_REG_RD(pDevice, Mailbox.RcvStdProdIdx.Low); + } + } +#if T3_JUMBO_RCV_RCB_ENTRY_COUNT + if(JumboBdAdded) + { + MB_REG_WR(pDevice, Mailbox.RcvJumboProdIdx.Low, + pDevice->RxJumboProdIdx); + if (pDevice->Flags & FLUSH_POSTED_WRITE_FLAG) + { + MB_REG_RD(pDevice, Mailbox.RcvJumboProdIdx.Low); + } + } +#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ + + return Lmstatus; +} /* LM_QueueRxPackets */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +STATIC LM_VOID +LM_NvramInit( + PLM_DEVICE_BLOCK pDevice) +{ + LM_UINT32 Value32; + + pDevice->NvramSize = 0; + /* Intialize clock period and state machine. */ + Value32 = SEEPROM_ADDR_CLK_PERD(SEEPROM_CLOCK_PERIOD) | + SEEPROM_ADDR_FSM_RESET; + REG_WR(pDevice, Grc.EepromAddr, Value32); + REG_RD_BACK(pDevice, Grc.EepromAddr); + + MM_Wait(100); + + /* Serial eeprom access using the Grc.EepromAddr/EepromData registers. */ + Value32 = REG_RD(pDevice, Grc.LocalCtrl); + REG_WR(pDevice, Grc.LocalCtrl, Value32 | GRC_MISC_LOCAL_CTRL_AUTO_SEEPROM); + + /* Set the 5701 compatibility mode if we are using EEPROM. */ + if(T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700 && + T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5701) + { + Value32 = REG_RD(pDevice, Nvram.Config1); + if((Value32 & FLASH_INTERFACE_ENABLE) == 0) + { + if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5750) + { + REG_WR(pDevice, Nvram.NvmAccess, + REG_RD(pDevice, Nvram.NvmAccess) | ACCESS_EN); + } + /* Use the new interface to read EEPROM. */ + Value32 &= ~FLASH_COMPAT_BYPASS; + + REG_WR(pDevice, Nvram.Config1, Value32); + + if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5750) + { + REG_WR(pDevice, Nvram.NvmAccess, + REG_RD(pDevice, Nvram.NvmAccess) & ~ACCESS_EN); + } + } + else { + pDevice->NvramSize = 0x20000; + pDevice->Flags |= FLASH_DETECTED_FLAG; + } + } + + if (pDevice->NvramSize == 0) + { + Value32 = 0; + LM_NvramRead(pDevice, 0, &Value32); + Value32 = MM_SWAP_BE32(Value32); + if (Value32 != 0x669955aa) { + pDevice->NvramSize = SEEPROM_CHIP_SIZE; + return; + } + + /* size eeprom */ + pDevice->NvramSize = 0x800; + while (pDevice->NvramSize < SEEPROM_CHIP_SIZE) { + if (LM_NvramRead(pDevice, pDevice->NvramSize, &Value32) != + LM_STATUS_SUCCESS) { + pDevice->NvramSize = SEEPROM_CHIP_SIZE; + break; + } + Value32 = MM_SWAP_BE32(Value32); + if (Value32 == 0x669955aa) + break; + pDevice->NvramSize <<= 1; + } + } +} /* LM_NvRamInit */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +STATIC LM_STATUS +LM_EepromRead( + PLM_DEVICE_BLOCK pDevice, + LM_UINT32 Offset, + LM_UINT32 *pData) +{ + LM_UINT32 Value32; + LM_UINT32 Addr; + LM_UINT32 Dev; + LM_UINT32 j; + + if(Offset > SEEPROM_CHIP_SIZE) + { + return LM_STATUS_FAILURE; + } + + Dev = Offset / SEEPROM_CHIP_SIZE; + Addr = Offset % SEEPROM_CHIP_SIZE; + + Value32 = REG_RD(pDevice, Grc.EepromAddr); + Value32 &= ~(SEEPROM_ADDR_ADDRESS_MASK | SEEPROM_ADDR_DEV_ID_MASK | + SEEPROM_ADDR_RW_MASK); + REG_WR(pDevice, Grc.EepromAddr, Value32 | SEEPROM_ADDR_DEV_ID(Dev) | + SEEPROM_ADDR_ADDRESS(Addr) | SEEPROM_ADDR_START | SEEPROM_ADDR_READ); + + for(j = 0; j < 1000; j++) + { + Value32 = REG_RD(pDevice, Grc.EepromAddr); + if(Value32 & SEEPROM_ADDR_COMPLETE) + { + break; + } + MM_Wait(20); + } + + if(Value32 & SEEPROM_ADDR_COMPLETE) + { + Value32 = REG_RD(pDevice, Grc.EepromData); + /* The endianess of the eeprom and flash interface is different */ + *pData = MM_SWAP_LE32(Value32); + + return LM_STATUS_SUCCESS; + } + + return LM_STATUS_FAILURE; +} /* LM_EepromRead */ + +#ifdef ETHTOOL_SEEPROM + +STATIC LM_STATUS +LM_EepromWriteBlock( + PLM_DEVICE_BLOCK pDevice, + LM_UINT32 Offset, + LM_UINT32 *pData, + LM_UINT32 Size) +{ + LM_UINT32 Value32 = 0; + LM_UINT32 Addr; + LM_UINT32 Dev; + LM_UINT32 i, j; + + if(Offset > SEEPROM_CHIP_SIZE) + { + return LM_STATUS_FAILURE; + } + + /* Enable EEPROM write. */ + if (pDevice->Flags & EEPROM_WP_FLAG) + { + REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl | + GRC_MISC_LOCAL_CTRL_GPIO_OE1); + REG_RD_BACK(pDevice, Grc.LocalCtrl); + MM_Wait(40); + + Value32 = REG_RD(pDevice, Grc.LocalCtrl); + if(Value32 & GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1) + { + return LM_STATUS_FAILURE; + } + } + + for (i = 0; i < Size ; i++, pData++, Offset += 4) { + + Dev = Offset / SEEPROM_CHIP_SIZE; + Addr = Offset % SEEPROM_CHIP_SIZE; + + /* Set the write value to the eeprom */ + REG_WR(pDevice, Grc.EepromData, MM_SWAP_LE32(*pData)); + + Value32 = REG_RD(pDevice, Grc.EepromAddr); + Value32 &= ~(SEEPROM_ADDR_ADDRESS_MASK | SEEPROM_ADDR_DEV_ID_MASK | + SEEPROM_ADDR_RW_MASK); + + REG_WR(pDevice, Grc.EepromAddr, Value32 | SEEPROM_ADDR_DEV_ID(Dev) | + SEEPROM_ADDR_ADDRESS(Addr) | SEEPROM_ADDR_START | SEEPROM_ADDR_WRITE); + + for(j = 0; j < 1000; j++) + { + Value32 = REG_RD(pDevice, Grc.EepromAddr); + if(Value32 & SEEPROM_ADDR_COMPLETE) + { + break; + } + MM_Wait(10); + } + } + + /* Write-protect EEPROM. */ + if (pDevice->Flags & EEPROM_WP_FLAG) + { + REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl | + GRC_MISC_LOCAL_CTRL_GPIO_OE1 | GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1); + REG_RD_BACK(pDevice, Grc.LocalCtrl); + MM_Wait(40); + } + + if(Value32 & SEEPROM_ADDR_COMPLETE) + { + return LM_STATUS_SUCCESS; + } + + return LM_STATUS_FAILURE; +} /* LM_EepromWriteBlock */ +#endif + +#define NVRAM_MAXWAIT 8000 +LM_STATUS +LM_NvramGetLock(LM_DEVICE_BLOCK *pDevice) +{ + int j; + + REG_WR(pDevice, Nvram.SwArb, SW_ARB_REQ_SET1); + /* worst case wait time for Nvram arbitration using serial eprom is */ + /* about 45 msec on a 5704 with the other channel loading boot code */ + for (j = 0; j < NVRAM_MAXWAIT; j++) + { + if (REG_RD(pDevice, Nvram.SwArb) & SW_ARB_GNT1) + { + break; + } + MM_Wait(20); + } + if (j == NVRAM_MAXWAIT) + { + return LM_STATUS_FAILURE; + } + return LM_STATUS_SUCCESS; +} + +LM_STATUS +LM_NvramReleaseLock(LM_DEVICE_BLOCK *pDevice) +{ + REG_WR(pDevice, Nvram.SwArb, SW_ARB_REQ_CLR1); + return LM_STATUS_SUCCESS; +} + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +LM_STATUS +LM_NvramRead( + PLM_DEVICE_BLOCK pDevice, + LM_UINT32 Offset, + LM_UINT32 *pData) +{ + LM_UINT32 Value32; + LM_STATUS Status; + LM_UINT32 j; + + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || + T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) + { + Status = LM_EepromRead(pDevice, Offset, pData); + } + else + { + /* Determine if we have flash or EEPROM. */ + Value32 = REG_RD(pDevice, Nvram.Config1); + if(Value32 & FLASH_INTERFACE_ENABLE) + { + if(Value32 & FLASH_SSRAM_BUFFERED_MODE) + { + Offset = ((Offset/BUFFERED_FLASH_PAGE_SIZE) << + BUFFERED_FLASH_PAGE_POS) + + (Offset % BUFFERED_FLASH_PAGE_SIZE); + } + } + + if (LM_NvramGetLock(pDevice) != LM_STATUS_SUCCESS) + { + return LM_STATUS_FAILURE; + } + + if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5750) + { + REG_WR(pDevice, Nvram.NvmAccess, + REG_RD(pDevice, Nvram.NvmAccess) | ACCESS_EN); + } + + /* Read from flash or EEPROM with the new 5703/02 interface. */ + REG_WR(pDevice, Nvram.Addr, Offset & NVRAM_ADDRESS_MASK); + + REG_WR(pDevice, Nvram.Cmd, NVRAM_CMD_RD | NVRAM_CMD_DO_IT | + NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE); + + /* Wait for the done bit to clear. */ + for(j = 0; j < 1000; j++) + { + MM_Wait(10); + + Value32 = REG_RD(pDevice, Nvram.Cmd); + if(Value32 & NVRAM_CMD_DONE) + { + MM_Wait(10); + + *pData = REG_RD(pDevice, Nvram.ReadData); + + /* Data is swapped so that the byte stream is the same */ + /* in big and little endian systems. */ + /* Caller will do additional swapping depending on */ + /* how it wants to look at the data. */ + *pData = MM_SWAP_BE32(*pData); + + break; + } + } + + LM_NvramReleaseLock(pDevice); + if(Value32 & NVRAM_CMD_DONE) + { + Status = LM_STATUS_SUCCESS; + } + else + { + Status = LM_STATUS_FAILURE; + } + } + + if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5750) + { + REG_WR(pDevice, Nvram.NvmAccess, + REG_RD(pDevice, Nvram.NvmAccess) & ~ACCESS_EN); + } + + return Status; +} /* LM_NvramRead */ + + +#ifdef ETHTOOL_SEEPROM +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +LM_STATUS +LM_NvramWriteBlock( + PLM_DEVICE_BLOCK pDevice, + LM_UINT32 Offset, + LM_UINT32 *pData, + LM_UINT32 Size) +{ + LM_UINT32 Value32 = 0; + LM_UINT32 ControlReg; + LM_UINT32 AddrOffset; + LM_STATUS Status; + LM_UINT32 i , j; + LM_UINT32 BufferedFlash; + + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || + T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) + { + Status = LM_EepromWriteBlock(pDevice, Offset, pData, Size); + } + else + { + if (LM_NvramGetLock(pDevice) != LM_STATUS_SUCCESS) + { + return LM_STATUS_FAILURE; + } + + if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5750) + { + REG_WR(pDevice, Nvram.NvmAccess, + REG_RD(pDevice, Nvram.NvmAccess) | ACCESS_EN); + } + + /* Enable EEPROM write. */ + if (pDevice->Flags & EEPROM_WP_FLAG) + { + REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl | + GRC_MISC_LOCAL_CTRL_GPIO_OE1); + REG_RD_BACK(pDevice, Grc.LocalCtrl); + MM_Wait(40); + + Value32 = REG_RD(pDevice, Grc.LocalCtrl); + if(Value32 & GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1) + { + if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5750) + { + REG_WR(pDevice, Nvram.NvmAccess, + REG_RD(pDevice, Nvram.NvmAccess) & ~ACCESS_EN); + } + return LM_STATUS_FAILURE; + } + } + + REG_WR(pDevice, Grc.Mode, pDevice->GrcMode | + GRC_MODE_NVRAM_WRITE_ENABLE); + + BufferedFlash = FALSE; + Value32 = REG_RD(pDevice, Nvram.Config1); + if(Value32 & FLASH_INTERFACE_ENABLE) + { + if(Value32 & FLASH_SSRAM_BUFFERED_MODE) + { + BufferedFlash = TRUE; + } + } + + for (i = 0 ; i < Size ; i++, pData++, Offset += 4) { + + /* Swap the data so that the byte stream will */ + /* be written the same in little and big endian systems */ + Value32 = MM_SWAP_BE32(*pData); + + /* set the desired write data value to the flash */ + REG_WR(pDevice, Nvram.WriteData, Value32); + + /* set targeted address */ + AddrOffset = Offset; + + /* Determine if we have flash or buffered flash. */ + if(BufferedFlash) + { + AddrOffset = ((Offset/BUFFERED_FLASH_PAGE_SIZE) << + BUFFERED_FLASH_PAGE_POS) + + (Offset % BUFFERED_FLASH_PAGE_SIZE); + } + + /* Write to flash or EEPROM with the new 5703/02 interface. */ + REG_WR(pDevice, Nvram.Addr, AddrOffset & NVRAM_ADDRESS_MASK); + + ControlReg = NVRAM_CMD_DO_IT | NVRAM_CMD_DONE | NVRAM_CMD_WR; + if(i == 0) + { + ControlReg |= NVRAM_CMD_FIRST; + } + if(i == (Size - 1)) + { + ControlReg |= NVRAM_CMD_LAST; + } + + if(BufferedFlash) + { + /* Set CMD_FIRST when we are at the beginning of a page. */ + if(!(AddrOffset & BUFFERED_FLASH_BYTE_ADDR_MASK)) + { + ControlReg |= NVRAM_CMD_FIRST; + } + else if((AddrOffset & BUFFERED_FLASH_BYTE_ADDR_MASK) == + (BUFFERED_FLASH_PAGE_SIZE - 4)) + { + ControlReg |= NVRAM_CMD_LAST; + } + } + + REG_WR(pDevice, Nvram.Cmd, ControlReg); + + /* Wait for the done bit to go High. */ + for(j = 0; j < 4000 ; j++) + { + MM_Wait(10); + + Value32 = REG_RD(pDevice, Nvram.Cmd); + + if(Value32 & NVRAM_CMD_DONE) + { + MM_Wait(5); + break; + } + } + } + + REG_WR(pDevice, Grc.Mode, pDevice->GrcMode); + + /* Write-protect EEPROM. */ + if(pDevice->Flags & EEPROM_WP_FLAG) + { + REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl | + GRC_MISC_LOCAL_CTRL_GPIO_OE1 | GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1); + REG_RD_BACK(pDevice, Grc.LocalCtrl); + MM_Wait(40); + } + + /* Relinquish nvram interface. */ + LM_NvramReleaseLock(pDevice); + + if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5750) + { + REG_WR(pDevice, Nvram.NvmAccess, + REG_RD(pDevice, Nvram.NvmAccess) & ~ACCESS_EN); + } + + if(Value32 & NVRAM_CMD_DONE) + { + Status = LM_STATUS_SUCCESS; + } + else + { + Status = LM_STATUS_FAILURE; + } + } + + return Status; +} /* LM_NvramWriteBlock */ +#endif + +STATIC void +LM_ReadVPD(PLM_DEVICE_BLOCK pDevice) +{ +#ifdef BCM_PROC_FS + LM_UINT32 Vpd_arr[256/4]; + LM_UINT8 *Vpd = (LM_UINT8 *) &Vpd_arr[0]; + LM_UINT32 *Vpd_dptr = &Vpd_arr[0]; + LM_UINT32 Value32; + unsigned int j; + + /* Read PN from VPD */ + for (j = 0; j < 256; j += 4, Vpd_dptr++ ) + { + if (LM_NvramRead(pDevice, 0x100 + j, &Value32) != LM_STATUS_SUCCESS) { + printf("VPD read failed\n"); + return; + } + *Vpd_dptr = Value32; + } + for (j = 0; j < 256; ) + { + unsigned int Vpd_r_len; + unsigned int Vpd_r_end; + + if ((Vpd[j] == 0x82) || (Vpd[j] == 0x91)) + { + j = j + 3 + Vpd[j + 1] + (Vpd[j + 2] << 8); + } + else if (Vpd[j] == 0x90) + { + Vpd_r_len = Vpd[j + 1] + (Vpd[j + 2] << 8); + j += 3; + Vpd_r_end = Vpd_r_len + j; + while (j < Vpd_r_end) + { + if ((Vpd[j] == 'P') && (Vpd[j + 1] == 'N')) + { + unsigned int len = Vpd[j + 2]; + + if (len <= 24) + { + memcpy(pDevice->PartNo, &Vpd[j + 3], len); + } + break; + } + else + { + if (Vpd[j + 2] == 0) + { + break; + } + j = j + Vpd[j + 2]; + } + } + break; + } + else { + break; + } + } +#endif +} + +STATIC void +LM_ReadBootCodeVersion(PLM_DEVICE_BLOCK pDevice) +{ +#ifdef BCM_PROC_FS + LM_UINT32 Value32, offset, ver_offset, start_addr; + int i; + + if (LM_NvramRead(pDevice, 0x0, &Value32) != LM_STATUS_SUCCESS) + return; + Value32 = MM_SWAP_BE32(Value32); + if (Value32 != 0x669955aa) + return; + if (LM_NvramRead(pDevice, 0xc, &offset) != LM_STATUS_SUCCESS) + return; + + offset = MM_SWAP_BE32(offset); + + if((T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700) && + (T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5701) && + ((REG_RD(pDevice, Nvram.Config1) & BUFFERED_FLASH) == BUFFERED_FLASH)) + { + offset = (offset >> BUFFERED_FLASH_PAGE_POS) * + BUFFERED_FLASH_PAGE_SIZE + (offset & BUFFERED_FLASH_BYTE_ADDR_MASK); + } + if (LM_NvramRead(pDevice, offset, &Value32) != LM_STATUS_SUCCESS) + return; + + Value32 = MM_SWAP_BE32(Value32); + if ((((Value32 & ~0x0f00) == 0x0e000003) || + ((Value32 & ~0xff00) == 0x0c000003)) && + (LM_NvramRead(pDevice, offset + 4, &Value32) == LM_STATUS_SUCCESS) && + (Value32 == 0)) { + + if (LM_NvramRead(pDevice, offset + 8, &ver_offset) != LM_STATUS_SUCCESS) + return; + if (LM_NvramRead(pDevice, 4, &start_addr) != LM_STATUS_SUCCESS) + return; + ver_offset = MM_SWAP_BE32(ver_offset); + start_addr = MM_SWAP_BE32(start_addr); + offset += ver_offset - start_addr; + for (i = 0; i < 16; i += 4) { + if (LM_NvramRead(pDevice, offset + i, &Value32) != + LM_STATUS_SUCCESS) + { + return; + } + *((LM_UINT32 *) &pDevice->BootCodeVer[i]) = Value32; + } + } + else { + char c; + + if (LM_NvramRead(pDevice, 0x94, &Value32) != LM_STATUS_SUCCESS) + return; + + Value32 = MM_SWAP_BE32(Value32); + i = 0; + c = ((Value32 & 0xff00) >> 8); + + if (c < 10) { + pDevice->BootCodeVer[i++] = c + '0'; + } + else { + pDevice->BootCodeVer[i++] = (c / 10) + '0'; + pDevice->BootCodeVer[i++] = (c % 10) + '0'; + } + pDevice->BootCodeVer[i++] = '.'; + c = Value32 & 0xff; + if (c < 10) { + pDevice->BootCodeVer[i++] = '0'; + pDevice->BootCodeVer[i++] = c + '0'; + } + else { + pDevice->BootCodeVer[i++] = (c / 10) + '0'; + pDevice->BootCodeVer[i++] = (c % 10) + '0'; + } + pDevice->BootCodeVer[i] = 0; + } +#endif +} + +STATIC void +LM_GetBusSpeed(PLM_DEVICE_BLOCK pDevice) +{ +#ifdef BCM_PROC_FS + LM_UINT32 PciState = pDevice->PciState; + LM_UINT32 ClockCtrl; + char *SpeedStr = ""; + + if (pDevice->Flags & PCI_EXPRESS_FLAG) + { + strcpy(pDevice->BusSpeedStr, "PCI Express"); + return; + } + if (PciState & T3_PCI_STATE_32BIT_PCI_BUS) + { + strcpy(pDevice->BusSpeedStr, "32-bit "); + } + else + { + strcpy(pDevice->BusSpeedStr, "64-bit "); + } + if (PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) + { + strcat(pDevice->BusSpeedStr, "PCI "); + if (PciState & T3_PCI_STATE_HIGH_BUS_SPEED) + { + SpeedStr = "66MHz"; + } + else + { + SpeedStr = "33MHz"; + } + } + else + { + strcat(pDevice->BusSpeedStr, "PCIX "); + if (pDevice->BondId == GRC_MISC_BD_ID_5704CIOBE) + { + SpeedStr = "133MHz"; + } + else + { + ClockCtrl = pDevice->ClockCtrl & 0x1f; + switch (ClockCtrl) + { + case 0: + SpeedStr = "33MHz"; + break; + + case 2: + SpeedStr = "50MHz"; + break; + + case 4: + SpeedStr = "66MHz"; + break; + + case 6: + SpeedStr = "100MHz"; + break; + + case 7: + SpeedStr = "133MHz"; + break; + } + } + } + strcat(pDevice->BusSpeedStr, SpeedStr); +#endif +} + +/******************************************************************************/ +/* Description: */ +/* This routine initializes default parameters and reads the PCI */ +/* configurations. */ +/* */ +/* Return: */ +/* LM_STATUS_SUCCESS */ +/******************************************************************************/ +LM_STATUS +LM_GetAdapterInfo( +PLM_DEVICE_BLOCK pDevice) +{ + PLM_ADAPTER_INFO pAdapterInfo; + LM_UINT32 Value32, LedCfg; + LM_STATUS Status; + LM_UINT32 EeSigFound; + LM_UINT32 EePhyTypeSerdes = 0; + LM_UINT32 EePhyId = 0; + + /* Get Device Id and Vendor Id */ + Status = MM_ReadConfig32(pDevice, PCI_VENDOR_ID_REG, &Value32); + if(Status != LM_STATUS_SUCCESS) + { + return Status; + } + pDevice->PciVendorId = (LM_UINT16) Value32; + pDevice->PciDeviceId = (LM_UINT16) (Value32 >> 16); + + Status = MM_ReadConfig32(pDevice, PCI_REV_ID_REG, &Value32); + if(Status != LM_STATUS_SUCCESS) + { + return Status; + } + pDevice->PciRevId = (LM_UINT8) Value32; + + /* Get chip revision id. */ + Status = MM_ReadConfig32(pDevice, T3_PCI_MISC_HOST_CTRL_REG, &Value32); + pDevice->ChipRevId = Value32 >> 16; + + /* detremine if it is PCIE system */ + if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5750) + { + Status = MM_ReadConfig32(pDevice, T3_MSI_CAPABILITY_ID_REG, &Value32); + if (((Value32 >> 8) & 0xff) == T3_PCIE_CAPABILITY_ID_REG) + { + Status = MM_ReadConfig32(pDevice, T3_PCIE_CAPABILITY_ID_REG, + &Value32); + if ((Value32 & 0xff) == T3_PCIE_CAPABILITY_ID) + { + pDevice->Flags |= PCI_EXPRESS_FLAG; + } + } + } + + /* Get subsystem vendor. */ + Status = MM_ReadConfig32(pDevice, PCI_SUBSYSTEM_VENDOR_ID_REG, &Value32); + if(Status != LM_STATUS_SUCCESS) + { + return Status; + } + pDevice->SubsystemVendorId = (LM_UINT16) Value32; + + /* Get PCI subsystem id. */ + pDevice->SubsystemId = (LM_UINT16) (Value32 >> 16); + + /* Get the cache line size. */ + MM_ReadConfig32(pDevice, PCI_CACHE_LINE_SIZE_REG, &Value32); + pDevice->CacheLineSize = (LM_UINT8) Value32; + pDevice->SavedCacheLineReg = Value32; + + if(pDevice->ChipRevId != T3_CHIP_ID_5703_A1 && + pDevice->ChipRevId != T3_CHIP_ID_5703_A2 && + pDevice->ChipRevId != T3_CHIP_ID_5704_A0) + { + pDevice->Flags &= ~UNDI_FIX_FLAG; + } +#if !PCIX_TARGET_WORKAROUND + pDevice->Flags &= ~UNDI_FIX_FLAG; +#endif + /* Map the memory base to system address space. */ + if (!(pDevice->Flags & UNDI_FIX_FLAG)) + { + Status = MM_MapMemBase(pDevice); + if(Status != LM_STATUS_SUCCESS) + { + return Status; + } + /* Initialize the memory view pointer. */ + pDevice->pMemView = (PT3_STD_MEM_MAP) pDevice->pMappedMemBase; + } + + if ((T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5700_BX) || + (T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5704_AX)) + { + pDevice->Flags |= TX_4G_WORKAROUND_FLAG; + } + if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) + { + pDevice->Flags |= REG_RD_BACK_FLAG; + } +#ifdef INCLUDE_5750_A0_FIX + if ((pDevice->Flags & PCI_EXPRESS_FLAG) && + (pDevice->ChipRevId == T3_CHIP_ID_5750_A0)) + { + pDevice->Flags |= REG_RD_BACK_FLAG; + } +#endif +#if PCIX_TARGET_WORKAROUND + MM_ReadConfig32(pDevice, T3_PCI_STATE_REG, &Value32); + if((Value32 & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) == 0) + { + /* Enable PCI-X workaround only if we are running on 5700 BX. */ + if(T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5700_BX) + { + pDevice->Flags |= ENABLE_PCIX_FIX_FLAG; + } + } + if (pDevice->Flags & UNDI_FIX_FLAG) + { + pDevice->Flags |= ENABLE_PCIX_FIX_FLAG; + } +#endif + /* Bx bug: due to the "byte_enable bug" in PCI-X mode, the power */ + /* management register may be clobbered which may cause the */ + /* BCM5700 to go into D3 state. While in this state, we will */ + /* not have memory mapped register access. As a workaround, we */ + /* need to restore the device to D0 state. */ + MM_ReadConfig32(pDevice, T3_PCI_PM_STATUS_CTRL_REG, &Value32); + Value32 |= T3_PM_PME_ASSERTED; + Value32 &= ~T3_PM_POWER_STATE_MASK; + Value32 |= T3_PM_POWER_STATE_D0; + MM_WriteConfig32(pDevice, T3_PCI_PM_STATUS_CTRL_REG, Value32); + + /* read the current PCI command word */ + MM_ReadConfig32(pDevice, PCI_COMMAND_REG, &Value32); + + /* Make sure bus-mastering is enabled. */ + Value32 |= PCI_BUSMASTER_ENABLE; + +#if PCIX_TARGET_WORKAROUND + /* if we are in PCI-X mode, also make sure mem-mapping and SERR#/PERR# + are enabled */ + if (pDevice->Flags & ENABLE_PCIX_FIX_FLAG) { + Value32 |= (PCI_MEM_SPACE_ENABLE | PCI_SYSTEM_ERROR_ENABLE | + PCI_PARITY_ERROR_ENABLE); + } + if (pDevice->Flags & UNDI_FIX_FLAG) + { + Value32 &= ~PCI_MEM_SPACE_ENABLE; + } + +#endif + + if (pDevice->Flags & ENABLE_MWI_FLAG) + { + Value32 |= PCI_MEMORY_WRITE_INVALIDATE; + } + else { + Value32 &= (~PCI_MEMORY_WRITE_INVALIDATE); + } + + /* save the value we are going to write into the PCI command word */ + pDevice->PciCommandStatusWords = Value32; + + Status = MM_WriteConfig32(pDevice, PCI_COMMAND_REG, Value32); + if(Status != LM_STATUS_SUCCESS) + { + return Status; + } + + /* Setup the mode registers. */ + pDevice->MiscHostCtrl = + MISC_HOST_CTRL_MASK_PCI_INT | + MISC_HOST_CTRL_ENABLE_ENDIAN_WORD_SWAP | +#ifdef BIG_ENDIAN_HOST + MISC_HOST_CTRL_ENABLE_ENDIAN_BYTE_SWAP | +#endif /* BIG_ENDIAN_HOST */ + MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS | + MISC_HOST_CTRL_ENABLE_PCI_STATE_REG_RW; + /* write to PCI misc host ctr first in order to enable indirect accesses */ + MM_WriteConfig32(pDevice, T3_PCI_MISC_HOST_CTRL_REG, pDevice->MiscHostCtrl); + + /* Set power state to D0. */ + LM_SetPowerState(pDevice, LM_POWER_STATE_D0); + + /* Preserve HOST_STACK_UP bit in case ASF firmware is running */ + Value32 = REG_RD(pDevice, Grc.Mode) & GRC_MODE_HOST_STACK_UP; +#ifdef BIG_ENDIAN_HOST + Value32 |= GRC_MODE_BYTE_SWAP_NON_FRAME_DATA | + GRC_MODE_WORD_SWAP_NON_FRAME_DATA; +#else + Value32 |= GRC_MODE_BYTE_SWAP_NON_FRAME_DATA | GRC_MODE_BYTE_SWAP_DATA; +#endif + REG_WR(pDevice, Grc.Mode, Value32); + + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) + { + REG_WR(pDevice, Grc.LocalCtrl, GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 | + GRC_MISC_LOCAL_CTRL_GPIO_OE1); + REG_RD_BACK(pDevice, Grc.LocalCtrl); + } + MM_Wait(40); + + /* Enable indirect memory access */ + REG_WR(pDevice, MemArbiter.Mode, T3_MEM_ARBITER_MODE_ENABLE); + + LM_SwitchClocks(pDevice); + + REG_WR(pDevice, PciCfg.MemWindowBaseAddr, 0); + + /* Check to see if PXE ran and did not shutdown properly */ + if ((REG_RD(pDevice, DmaWrite.Mode) & DMA_WRITE_MODE_ENABLE) || + !(REG_RD(pDevice, PciCfg.MiscHostCtrl) & MISC_HOST_CTRL_MASK_PCI_INT)) + { + LM_DisableInterrupt(pDevice); + /* assume ASF is enabled */ + pDevice->AsfFlags = ASF_ENABLED; + if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5750) + { + pDevice->AsfFlags |= ASF_NEW_HANDSHAKE; + } + LM_ShutdownChip(pDevice, LM_SHUTDOWN_RESET); + pDevice->AsfFlags = 0; + } +#if PCIX_TARGET_WORKAROUND + MM_ReadConfig32(pDevice, T3_PCI_STATE_REG, &Value32); + if (!(pDevice->Flags & ENABLE_PCIX_FIX_FLAG) && + ((Value32 & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) == 0)) + { + if (pDevice->ChipRevId == T3_CHIP_ID_5701_A0 || + pDevice->ChipRevId == T3_CHIP_ID_5701_B0 || + pDevice->ChipRevId == T3_CHIP_ID_5701_B2 || + pDevice->ChipRevId == T3_CHIP_ID_5701_B5) + { + MM_MEMWRITEL(&(pDevice->pMemView->uIntMem.MemBlock32K[0x300]), 0); + MM_MEMWRITEL(&(pDevice->pMemView->uIntMem.MemBlock32K[0x301]), 0); + MM_MEMWRITEL(&(pDevice->pMemView->uIntMem.MemBlock32K[0x301]), + 0xffffffff); + if (MM_MEMREADL(&(pDevice->pMemView->uIntMem.MemBlock32K[0x300]))) + { + pDevice->Flags |= ENABLE_PCIX_FIX_FLAG; + } + } + } +#endif + + LM_NvramInit(pDevice); + + Status = LM_STATUS_FAILURE; + /* Get the node address. First try to get in from the shared memory. */ + /* If the signature is not present, then get it from the NVRAM. */ + Value32 = MEM_RD_OFFSET(pDevice, T3_MAC_ADDR_HIGH_MAILBOX); + if((Value32 >> 16) == 0x484b) + { + int i; + + pDevice->NodeAddress[0] = (LM_UINT8) (Value32 >> 8); + pDevice->NodeAddress[1] = (LM_UINT8) Value32; + + Value32 = MEM_RD_OFFSET(pDevice, T3_MAC_ADDR_LOW_MAILBOX); + + pDevice->NodeAddress[2] = (LM_UINT8) (Value32 >> 24); + pDevice->NodeAddress[3] = (LM_UINT8) (Value32 >> 16); + pDevice->NodeAddress[4] = (LM_UINT8) (Value32 >> 8); + pDevice->NodeAddress[5] = (LM_UINT8) Value32; + + /* Check for null MAC address which can happen with older boot code */ + for (i = 0; i < 6; i++) + { + if (pDevice->NodeAddress[i] != 0) + { + Status = LM_STATUS_SUCCESS; + break; + } + } + } + if (Status != LM_STATUS_SUCCESS) + { + int MacOffset; + + MacOffset = 0x7c; + if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704) + { + if (REG_RD(pDevice, PciCfg.DualMacCtrl) & T3_DUAL_MAC_ID) + { + MacOffset = 0xcc; + } + /* workaround - need to reset nvram if */ + /* the boot code is not running */ + if (LM_NvramGetLock(pDevice) != LM_STATUS_SUCCESS) + { + REG_WR(pDevice, Nvram.Cmd, NVRAM_CMD_RESET); + } + else + { + LM_NvramReleaseLock(pDevice); + } + } + Status = LM_NvramRead(pDevice, MacOffset, &Value32); + if(Status == LM_STATUS_SUCCESS) + { + LM_UINT8 *c = (LM_UINT8 *) &Value32; + + pDevice->NodeAddress[0] = c[2]; + pDevice->NodeAddress[1] = c[3]; + + Status = LM_NvramRead(pDevice, MacOffset + 4, &Value32); + + c = (LM_UINT8 *) &Value32; + pDevice->NodeAddress[2] = c[0]; + pDevice->NodeAddress[3] = c[1]; + pDevice->NodeAddress[4] = c[2]; + pDevice->NodeAddress[5] = c[3]; + } + } + + if(Status != LM_STATUS_SUCCESS) + { + Value32 = REG_RD(pDevice, MacCtrl.MacAddr[0].High); + pDevice->NodeAddress[0] = (Value32 >> 8) & 0xff; + pDevice->NodeAddress[1] = Value32 & 0xff; + Value32 = REG_RD(pDevice, MacCtrl.MacAddr[0].Low); + pDevice->NodeAddress[2] = (Value32 >> 24) & 0xff; + pDevice->NodeAddress[3] = (Value32 >> 16) & 0xff; + pDevice->NodeAddress[4] = (Value32 >> 8) & 0xff; + pDevice->NodeAddress[5] = Value32 & 0xff; + printf("WARNING: Cannot get MAC addr from NVRAM, using %2.2x%2.2x%2.2x%2.2x%2.2x%2.2x\n", + pDevice->NodeAddress[0], pDevice->NodeAddress[1], + pDevice->NodeAddress[2], pDevice->NodeAddress[3], + pDevice->NodeAddress[4], pDevice->NodeAddress[5]); + } + + memcpy(pDevice->PermanentNodeAddress, pDevice->NodeAddress, 6); + + /* Initialize the default values. */ + pDevice->TxPacketDescCnt = DEFAULT_TX_PACKET_DESC_COUNT; + pDevice->RxStdDescCnt = DEFAULT_STD_RCV_DESC_COUNT; + pDevice->RxCoalescingTicks = DEFAULT_RX_COALESCING_TICKS; + pDevice->TxCoalescingTicks = DEFAULT_TX_COALESCING_TICKS; + pDevice->RxMaxCoalescedFrames = DEFAULT_RX_MAX_COALESCED_FRAMES; + pDevice->TxMaxCoalescedFrames = DEFAULT_TX_MAX_COALESCED_FRAMES; + pDevice->RxCoalescingTicksDuringInt = BAD_DEFAULT_VALUE; + pDevice->TxCoalescingTicksDuringInt = BAD_DEFAULT_VALUE; + pDevice->RxMaxCoalescedFramesDuringInt = BAD_DEFAULT_VALUE; + pDevice->TxMaxCoalescedFramesDuringInt = BAD_DEFAULT_VALUE; + pDevice->StatsCoalescingTicks = DEFAULT_STATS_COALESCING_TICKS; + pDevice->TxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC; + pDevice->RxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC; + pDevice->DisableAutoNeg = FALSE; + pDevice->PhyIntMode = T3_PHY_INT_MODE_AUTO; + pDevice->LinkChngMode = T3_LINK_CHNG_MODE_AUTO; + + pDevice->PhyFlags = 0; + + if (!(pDevice->Flags & PCI_EXPRESS_FLAG)) + pDevice->Flags |= DELAY_PCI_GRANT_FLAG; + + pDevice->RequestedLineSpeed = LM_LINE_SPEED_AUTO; + pDevice->TaskOffloadCap = LM_TASK_OFFLOAD_NONE; + pDevice->TaskToOffload = LM_TASK_OFFLOAD_NONE; + pDevice->FlowControlCap = LM_FLOW_CONTROL_AUTO_PAUSE; +#if INCLUDE_TBI_SUPPORT + pDevice->TbiFlags = 0; + pDevice->IgnoreTbiLinkChange = FALSE; +#endif +#if INCLUDE_TCP_SEG_SUPPORT + pDevice->LargeSendMaxSize = T3_TCP_SEG_MAX_OFFLOAD_SIZE; + pDevice->LargeSendMinNumSeg = T3_TCP_SEG_MIN_NUM_SEG; +#endif + + if ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703) || + (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704) || + (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5705)) + { + pDevice->PhyFlags |= PHY_RESET_ON_LINKDOWN; + pDevice->PhyFlags |= PHY_CHECK_TAPS_AFTER_RESET; + } + if ((T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5703_AX) || + (T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5704_AX)) + { + pDevice->PhyFlags |= PHY_ADC_FIX; + } + if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0) + { + pDevice->PhyFlags |= PHY_5704_A0_FIX; + } + if (T3_ASIC_5705_OR_5750(pDevice->ChipRevId)) + { + pDevice->PhyFlags |= PHY_5705_5750_FIX; + } + /* Ethernet@Wirespeed is supported on 5701,5702,5703,5704,5705a0,5705a1 */ + if ((T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700) && + !((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5705) && + (pDevice->ChipRevId != T3_CHIP_ID_5705_A0) && + (pDevice->ChipRevId != T3_CHIP_ID_5705_A1))) + { + pDevice->PhyFlags |= PHY_ETHERNET_WIRESPEED; + } + + switch (T3_ASIC_REV(pDevice->ChipRevId)) + { + case T3_ASIC_REV_5704: + pDevice->MbufBase = T3_NIC_MBUF_POOL_ADDR; + pDevice->MbufSize = T3_NIC_MBUF_POOL_SIZE64; + break; + default: + pDevice->MbufBase = T3_NIC_MBUF_POOL_ADDR; + pDevice->MbufSize = T3_NIC_MBUF_POOL_SIZE96; + break; + } + + pDevice->LinkStatus = LM_STATUS_LINK_DOWN; + pDevice->QueueRxPackets = TRUE; + +#if T3_JUMBO_RCV_RCB_ENTRY_COUNT + pDevice->RxJumboDescCnt = DEFAULT_JUMBO_RCV_DESC_COUNT; + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5705) + { + pDevice->RxJumboDescCnt = 0; + } +#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ + + pDevice->BondId = REG_RD(pDevice, Grc.MiscCfg) & GRC_MISC_BD_ID_MASK; + + if(((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) && + ((pDevice->BondId == 0x10000) || (pDevice->BondId == 0x18000))) || + ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703) && + ((pDevice->BondId == 0x14000) || (pDevice->BondId == 0x1c000)))) + { + return LM_STATUS_UNKNOWN_ADAPTER; + } + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703) + { + if ((pDevice->BondId == 0x8000) || (pDevice->BondId == 0x4000)) + { + pDevice->PhyFlags |= PHY_NO_GIGABIT; + } + } + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5705) + { + if ((pDevice->BondId == GRC_MISC_BD_ID_5788) || + (pDevice->BondId == GRC_MISC_BD_ID_5788M)) + { + pDevice->Flags |= BCM5788_FLAG; + } + if ((pDevice->PciDeviceId == T3_PCI_DEVICE_ID(T3_PCI_ID_BCM5901)) || + (pDevice->PciDeviceId == T3_PCI_DEVICE_ID(T3_PCI_ID_BCM5901A2)) || + (pDevice->PciDeviceId == T3_PCI_DEVICE_ID(T3_PCI_ID_BCM5705F))) + { + pDevice->PhyFlags |= PHY_NO_GIGABIT; + } + } + if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5750) + { + if (pDevice->PciDeviceId == T3_PCI_DEVICE_ID(T3_PCI_ID_BCM5751F)) + { + pDevice->PhyFlags |= PHY_NO_GIGABIT; + } + } + + /* CIOBE multisplit has a bug */ +#if 0 + if ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704) && + (pDevice->BondId == GRC_MISC_BD_ID_5704CIOBE)) + { + pDevice->Flags |= MULTI_SPLIT_ENABLE_FLAG; + pDevice->SplitModeMaxReq = SPLIT_MODE_5704_MAX_REQ; + } +#endif + + /* Get Eeprom info. */ + Value32 = MEM_RD_OFFSET(pDevice, T3_NIC_DATA_SIG_ADDR); + if (Value32 == T3_NIC_DATA_SIG) + { + EeSigFound = TRUE; + Value32 = MEM_RD_OFFSET(pDevice, T3_NIC_DATA_NIC_CFG_ADDR); + + if (Value32 & T3_NIC_MINI_PCI) + { + pDevice->Flags |= MINI_PCI_FLAG; + } + /* Determine PHY type. */ + switch (Value32 & T3_NIC_CFG_PHY_TYPE_MASK) + { + case T3_NIC_CFG_PHY_TYPE_COPPER: + EePhyTypeSerdes = FALSE; + break; + + case T3_NIC_CFG_PHY_TYPE_FIBER: + EePhyTypeSerdes = TRUE; + break; + + default: + EePhyTypeSerdes = FALSE; + break; + } + + if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5750) + { + LedCfg = MEM_RD_OFFSET(pDevice, T3_NIC_DATA_NIC_CFG_ADDR2); + LedCfg = LedCfg & (T3_NIC_CFG_LED_MODE_MASK | + T3_SHASTA_EXT_LED_MODE_MASK); + } + else + { + /* Determine PHY led mode. for legacy devices */ + LedCfg = Value32 & T3_NIC_CFG_LED_MODE_MASK; + } + + switch (LedCfg) + { + default: + case T3_NIC_CFG_LED_PHY_MODE_1: + pDevice->LedCtrl = LED_CTRL_PHY_MODE_1; + break; + + case T3_NIC_CFG_LED_PHY_MODE_2: + pDevice->LedCtrl = LED_CTRL_PHY_MODE_2; + break; + + case T3_NIC_CFG_LED_MAC_MODE: + pDevice->LedCtrl = LED_CTRL_MAC_MODE; + break; + + case T3_SHASTA_EXT_LED_SHARED_TRAFFIC_LINK_MODE: + pDevice->LedCtrl = LED_CTRL_SHARED_TRAFFIC_LINK; + if ((pDevice->ChipRevId != T3_CHIP_ID_5750_A0) && + (pDevice->ChipRevId != T3_CHIP_ID_5750_A1)) + { + pDevice->LedCtrl |= LED_CTRL_PHY_MODE_1 | + LED_CTRL_PHY_MODE_2; + } + break; + + case T3_SHASTA_EXT_LED_MAC_MODE: + pDevice->LedCtrl = LED_CTRL_SHASTA_MAC_MODE; + break; + + case T3_SHASTA_EXT_LED_WIRELESS_COMBO_MODE: + pDevice->LedCtrl = LED_CTRL_WIRELESS_COMBO; + if (pDevice->ChipRevId != T3_CHIP_ID_5750_A0) + { + pDevice->LedCtrl |= LED_CTRL_PHY_MODE_1 | + LED_CTRL_PHY_MODE_2; + } + break; + + } + + if (((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || + T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701)) && + (pDevice->SubsystemVendorId == T3_SVID_DELL)) + { + pDevice->LedCtrl = LED_CTRL_PHY_MODE_2; + } + + if((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703) || + (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704) || + (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5705)) + { + /* Enable EEPROM write protection. */ + if(Value32 & T3_NIC_EEPROM_WP) + { + pDevice->Flags |= EEPROM_WP_FLAG; + } + } + pDevice->AsfFlags = 0; +#ifdef BCM_ASF + if (Value32 & T3_NIC_CFG_ENABLE_ASF) + { + pDevice->AsfFlags |= ASF_ENABLED; + if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5750) + { + pDevice->AsfFlags |= ASF_NEW_HANDSHAKE; + } + } +#endif + if (Value32 & T3_NIC_FIBER_WOL_CAPABLE) + { + pDevice->Flags |= FIBER_WOL_CAPABLE_FLAG; + } + if (Value32 & T3_NIC_WOL_LIMIT_10) + { + pDevice->Flags |= WOL_LIMIT_10MBPS_FLAG; + } + + /* Get the PHY Id. */ + Value32 = MEM_RD_OFFSET(pDevice, T3_NIC_DATA_PHY_ID_ADDR); + if (Value32) + { + EePhyId = (((Value32 & T3_NIC_PHY_ID1_MASK) >> 16) & + PHY_ID1_OUI_MASK) << 10; + + Value32 = Value32 & T3_NIC_PHY_ID2_MASK; + + EePhyId |= ((Value32 & PHY_ID2_OUI_MASK) << 16) | + (Value32 & PHY_ID2_MODEL_MASK) | (Value32 & PHY_ID2_REV_MASK); + } + else + { + EePhyId = 0; + if (!EePhyTypeSerdes && !(pDevice->AsfFlags & ASF_ENABLED)) + { + /* reset PHY if boot code couldn't read the PHY ID */ + LM_ResetPhy(pDevice); + } + } + if (MEM_RD_OFFSET(pDevice, T3_NIC_DATA_NIC_CFG_ADDR2) & BIT_17) + { + pDevice->PhyFlags |= PHY_CAPACITIVE_COUPLING; + } + } + else + { + EeSigFound = FALSE; + } + + /* Set the PHY address. */ + pDevice->PhyAddr = PHY_DEVICE_ID; + + /* Disable auto polling. */ + pDevice->MiMode = 0xc0000; + REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode); + REG_RD_BACK(pDevice, MacCtrl.MiMode); + MM_Wait(80); + + if (pDevice->AsfFlags & ASF_ENABLED) + { + /* Reading PHY registers will contend with ASF */ + pDevice->PhyId = 0; + } + else + { + /* Get the PHY id. */ + LM_GetPhyId(pDevice); + } + + /* Set the EnableTbi flag to false if we have a copper PHY. */ + switch(pDevice->PhyId & PHY_ID_MASK) + { + case PHY_BCM5400_PHY_ID: + case PHY_BCM5401_PHY_ID: + case PHY_BCM5411_PHY_ID: + case PHY_BCM5701_PHY_ID: + case PHY_BCM5703_PHY_ID: + case PHY_BCM5704_PHY_ID: + case PHY_BCM5705_PHY_ID: + case PHY_BCM5750_PHY_ID: + break; + + case PHY_BCM8002_PHY_ID: + pDevice->TbiFlags |= ENABLE_TBI_FLAG; + break; + + default: + + if (EeSigFound) + { + pDevice->PhyId = EePhyId; + if (EePhyTypeSerdes) + { + pDevice->TbiFlags |= ENABLE_TBI_FLAG; + } + } + else if ((pAdapterInfo = LM_GetAdapterInfoBySsid( + pDevice->SubsystemVendorId, + pDevice->SubsystemId))) + { + pDevice->PhyId = pAdapterInfo->PhyId; + if (pAdapterInfo->Serdes) + { + pDevice->TbiFlags |= ENABLE_TBI_FLAG; + } + } + else + { + if (UNKNOWN_PHY_ID(pDevice->PhyId)) + { + LM_ResetPhy(pDevice); + LM_GetPhyId(pDevice); + } + } + break; + } + + if(UNKNOWN_PHY_ID(pDevice->PhyId) && + !(pDevice->TbiFlags & ENABLE_TBI_FLAG)) + { + pDevice->TbiFlags |= ENABLE_TBI_FLAG; + printf("PHY ID unknown, assume it is SerDes\n"); + } + + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703) + { + if((pDevice->SavedCacheLineReg & 0xff00) < 0x4000) + { + pDevice->SavedCacheLineReg &= 0xffff00ff; + pDevice->SavedCacheLineReg |= 0x4000; + } + } + + pDevice->ReceiveMask = LM_ACCEPT_MULTICAST | LM_ACCEPT_BROADCAST | + LM_ACCEPT_UNICAST; + + pDevice->TaskOffloadCap = LM_TASK_OFFLOAD_TX_TCP_CHECKSUM | + LM_TASK_OFFLOAD_TX_UDP_CHECKSUM | LM_TASK_OFFLOAD_RX_TCP_CHECKSUM | + LM_TASK_OFFLOAD_RX_UDP_CHECKSUM; + + if (pDevice->ChipRevId == T3_CHIP_ID_5700_B0) + { + pDevice->TaskOffloadCap &= ~(LM_TASK_OFFLOAD_TX_TCP_CHECKSUM | + LM_TASK_OFFLOAD_TX_UDP_CHECKSUM); + } + +#if INCLUDE_TCP_SEG_SUPPORT + pDevice->TaskOffloadCap |= LM_TASK_OFFLOAD_TCP_SEGMENTATION; + + if ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) || + (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) || + (pDevice->ChipRevId == T3_CHIP_ID_5705_A0)) + { + pDevice->TaskOffloadCap &= ~LM_TASK_OFFLOAD_TCP_SEGMENTATION; + } +#endif + +#ifdef BCM_ASF + if (pDevice->AsfFlags & ASF_ENABLED) + { + if (T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5750) + { + pDevice->TaskOffloadCap &= ~LM_TASK_OFFLOAD_TCP_SEGMENTATION; + } + } +#endif + + /* Change driver parameters. */ + Status = MM_GetConfig(pDevice); + if(Status != LM_STATUS_SUCCESS) + { + return Status; + } + + if (T3_ASIC_5705_OR_5750(pDevice->ChipRevId)) + { + pDevice->Flags &= ~NIC_SEND_BD_FLAG; + } + + /* Save the current phy link status. */ + if (!(pDevice->TbiFlags & ENABLE_TBI_FLAG) && + !(pDevice->AsfFlags & ASF_ENABLED)) + { + LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); + LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); + + /* If we don't have link reset the PHY. */ + if(!(Value32 & PHY_STATUS_LINK_PASS) || + (pDevice->PhyFlags & PHY_RESET_ON_INIT)) + { + + LM_ResetPhy(pDevice); + + if (LM_PhyAdvertiseAll(pDevice) != LM_STATUS_SUCCESS) + { + Value32 = PHY_AN_AD_PROTOCOL_802_3_CSMA_CD | + PHY_AN_AD_ALL_SPEEDS; + Value32 |= GetPhyAdFlowCntrlSettings(pDevice); + LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32); + + Value32 = BCM540X_AN_AD_ALL_1G_SPEEDS ; +#if INCLUDE_5701_AX_FIX + if(pDevice->ChipRevId == T3_CHIP_ID_5701_A0 || + pDevice->ChipRevId == T3_CHIP_ID_5701_B0) + { + Value32 |= BCM540X_CONFIG_AS_MASTER | + BCM540X_ENABLE_CONFIG_AS_MASTER; + } +#endif + LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, Value32); + + LM_WritePhy(pDevice, PHY_CTRL_REG, PHY_CTRL_AUTO_NEG_ENABLE | + PHY_CTRL_RESTART_AUTO_NEG); + } + + } + LM_SetEthWireSpeed(pDevice); + + LM_ReadPhy(pDevice, PHY_AN_AD_REG, &pDevice->advertising); + LM_ReadPhy(pDevice, BCM540X_1000BASET_CTRL_REG, + &pDevice->advertising1000); + } + LM_PhyTapPowerMgmt(pDevice); + +#if INCLUDE_TBI_SUPPORT + if(pDevice->TbiFlags & ENABLE_TBI_FLAG) + { + if (!(pDevice->Flags & FIBER_WOL_CAPABLE_FLAG)) + { + pDevice->WakeUpModeCap = LM_WAKE_UP_MODE_NONE; + } + pDevice->PhyIntMode = T3_PHY_INT_MODE_LINK_READY; + if (pDevice->TbiFlags & TBI_PURE_POLLING_FLAG) + { + pDevice->IgnoreTbiLinkChange = TRUE; + } + } + else + { + pDevice->TbiFlags = 0; + } +#endif /* INCLUDE_TBI_SUPPORT */ + + /* UseTaggedStatus is only valid for 5701 and later. */ + if ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) || + ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5705) && + ((pDevice->BondId == GRC_MISC_BD_ID_5788) || + (pDevice->BondId == GRC_MISC_BD_ID_5788M)))) + { + pDevice->Flags &= ~USE_TAGGED_STATUS_FLAG; + pDevice->CoalesceMode = 0; + } + else + { + pDevice->CoalesceMode = HOST_COALESCE_CLEAR_TICKS_ON_RX_BD_EVENT | + HOST_COALESCE_CLEAR_TICKS_ON_TX_BD_EVENT; + } + + /* Set the status block size. */ + if(T3_CHIP_REV(pDevice->ChipRevId) != T3_CHIP_REV_5700_AX && + T3_CHIP_REV(pDevice->ChipRevId) != T3_CHIP_REV_5700_BX) + { + pDevice->CoalesceMode |= HOST_COALESCE_32_BYTE_STATUS_MODE; + } + + /* Check the DURING_INT coalescing ticks parameters. */ + if (pDevice->Flags & USE_TAGGED_STATUS_FLAG) + { + if(pDevice->RxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE) + { + pDevice->RxCoalescingTicksDuringInt = + DEFAULT_RX_COALESCING_TICKS_DURING_INT; + } + + if(pDevice->TxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE) + { + pDevice->TxCoalescingTicksDuringInt = + DEFAULT_TX_COALESCING_TICKS_DURING_INT; + } + + if(pDevice->RxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE) + { + pDevice->RxMaxCoalescedFramesDuringInt = + DEFAULT_RX_MAX_COALESCED_FRAMES_DURING_INT; + } + + if(pDevice->TxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE) + { + pDevice->TxMaxCoalescedFramesDuringInt = + DEFAULT_TX_MAX_COALESCED_FRAMES_DURING_INT; + } + } + else + { + if(pDevice->RxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE) + { + pDevice->RxCoalescingTicksDuringInt = 0; + } + + if(pDevice->TxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE) + { + pDevice->TxCoalescingTicksDuringInt = 0; + } + + if(pDevice->RxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE) + { + pDevice->RxMaxCoalescedFramesDuringInt = 0; + } + + if(pDevice->TxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE) + { + pDevice->TxMaxCoalescedFramesDuringInt = 0; + } + } + +#if T3_JUMBO_RCV_RCB_ENTRY_COUNT + if(pDevice->RxMtu <= (MAX_STD_RCV_BUFFER_SIZE - 8 /* CRC */)) + { + pDevice->RxJumboDescCnt = 0; + if(pDevice->RxMtu <= MAX_ETHERNET_PACKET_SIZE_NO_CRC) + { + pDevice->RxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC; + } + } + else if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5705) + { + pDevice->RxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC; + pDevice->RxJumboDescCnt = 0; + } + else + { + pDevice->RxJumboBufferSize = (pDevice->RxMtu + 8 /* CRC + VLAN */ + + COMMON_CACHE_LINE_SIZE-1) & ~COMMON_CACHE_LINE_MASK; + + if(pDevice->RxJumboBufferSize > MAX_JUMBO_RCV_BUFFER_SIZE) + { + pDevice->RxJumboBufferSize = DEFAULT_JUMBO_RCV_BUFFER_SIZE; + pDevice->RxMtu = pDevice->RxJumboBufferSize - 8 /* CRC + VLAN */; + } + pDevice->TxMtu = pDevice->RxMtu; + + } +#else + pDevice->RxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC; +#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ + + pDevice->RxPacketDescCnt = +#if T3_JUMBO_RCV_RCB_ENTRY_COUNT + pDevice->RxJumboDescCnt + +#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ + pDevice->RxStdDescCnt; + + if(pDevice->TxMtu < MAX_ETHERNET_PACKET_SIZE_NO_CRC) + { + pDevice->TxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC; + } + + if(pDevice->TxMtu > MAX_JUMBO_TX_BUFFER_SIZE) + { + pDevice->TxMtu = MAX_JUMBO_TX_BUFFER_SIZE; + } + + /* Configure the proper ways to get link change interrupt. */ + if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO) + { + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) + { + pDevice->PhyIntMode = T3_PHY_INT_MODE_MI_INTERRUPT; + } + else + { + pDevice->PhyIntMode = T3_PHY_INT_MODE_LINK_READY; + } + } + else if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) + { + /* Auto-polling does not work on 5700_AX and 5700_BX. */ + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) + { + pDevice->PhyIntMode = T3_PHY_INT_MODE_MI_INTERRUPT; + } + } + + /* Determine the method to get link change status. */ + if(pDevice->LinkChngMode == T3_LINK_CHNG_MODE_AUTO) + { + /* The link status bit in the status block does not work on 5700_AX */ + /* and 5700_BX chips. */ + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) + { + pDevice->LinkChngMode = T3_LINK_CHNG_MODE_USE_STATUS_REG; + } + else + { + pDevice->LinkChngMode = T3_LINK_CHNG_MODE_USE_STATUS_BLOCK; + } + } + + if(pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT || + T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) + { + pDevice->LinkChngMode = T3_LINK_CHNG_MODE_USE_STATUS_REG; + } + + if (!EeSigFound) + { + pDevice->LedCtrl = LED_CTRL_PHY_MODE_1; + } + + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || + T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) + { + /* bug? 5701 in LINK10 mode does not seem to work when */ + /* PhyIntMode is LINK_READY. */ + if(T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700 && +#if INCLUDE_TBI_SUPPORT + !(pDevice->TbiFlags & ENABLE_TBI_FLAG) && +#endif + pDevice->LedCtrl == LED_CTRL_PHY_MODE_2) + { + pDevice->PhyIntMode = T3_PHY_INT_MODE_MI_INTERRUPT; + pDevice->LinkChngMode = T3_LINK_CHNG_MODE_USE_STATUS_REG; + } + if (pDevice->TbiFlags & ENABLE_TBI_FLAG) + { + pDevice->LedCtrl = LED_CTRL_PHY_MODE_1; + } + } + +#ifdef BCM_WOL + if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || + pDevice->ChipRevId == T3_CHIP_ID_5701_A0 || + pDevice->ChipRevId == T3_CHIP_ID_5701_B0 || + pDevice->ChipRevId == T3_CHIP_ID_5701_B2) + { + pDevice->WolSpeed = WOL_SPEED_10MB; + } + else + { + if (pDevice->Flags & WOL_LIMIT_10MBPS_FLAG) + { + pDevice->WolSpeed = WOL_SPEED_10MB; + } + else + { + pDevice->WolSpeed = WOL_SPEED_100MB; + } + } +#endif + + pDevice->PciState = REG_RD(pDevice, PciCfg.PciState); + + pDevice->DmaReadFifoSize = 0; + if (((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5705) && + (pDevice->ChipRevId != T3_CHIP_ID_5705_A0)) || + (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5750)) + { +#if INCLUDE_TCP_SEG_SUPPORT + if ((pDevice->TaskToOffload & LM_TASK_OFFLOAD_TCP_SEGMENTATION) && + ((pDevice->ChipRevId == T3_CHIP_ID_5705_A1) || + (pDevice->ChipRevId == T3_CHIP_ID_5705_A2))) + { + pDevice->DmaReadFifoSize = DMA_READ_MODE_FIFO_SIZE_128; + } + else +#endif + { + if (!(pDevice->PciState & T3_PCI_STATE_HIGH_BUS_SPEED) && + !(pDevice->Flags & BCM5788_FLAG) && + !(pDevice->Flags & PCI_EXPRESS_FLAG)) + { + pDevice->DmaReadFifoSize = DMA_READ_MODE_FIFO_LONG_BURST; + if (pDevice->ChipRevId == T3_CHIP_ID_5705_A1) + { + pDevice->Flags |= RX_BD_LIMIT_64_FLAG; + } + pDevice->Flags |= DMA_WR_MODE_RX_ACCELERATE_FLAG; + } + else if (pDevice->Flags & PCI_EXPRESS_FLAG) + { + pDevice->DmaReadFifoSize = DMA_READ_MODE_FIFO_LONG_BURST; + } + } + } + + LM_ReadVPD(pDevice); + LM_ReadBootCodeVersion(pDevice); + LM_GetBusSpeed(pDevice); + + return LM_STATUS_SUCCESS; +} /* LM_GetAdapterInfo */ + +STATIC PLM_ADAPTER_INFO +LM_GetAdapterInfoBySsid( + LM_UINT16 Svid, + LM_UINT16 Ssid) +{ + static LM_ADAPTER_INFO AdapterArr[] = + { + { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95700A6, PHY_BCM5401_PHY_ID, 0}, + { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A5, PHY_BCM5701_PHY_ID, 0}, + { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95700T6, PHY_BCM8002_PHY_ID, 1}, + { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95700A9, 0, 1 }, + { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701T1, PHY_BCM5701_PHY_ID, 0}, + { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701T8, PHY_BCM5701_PHY_ID, 0}, + { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A7, 0, 1}, + { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A10, PHY_BCM5701_PHY_ID, 0}, + { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A12, PHY_BCM5701_PHY_ID, 0}, + { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95703Ax1, PHY_BCM5703_PHY_ID, 0}, + { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95703Ax2, PHY_BCM5703_PHY_ID, 0}, + + { T3_SVID_3COM, T3_SSID_3COM_3C996T, PHY_BCM5401_PHY_ID, 0 }, + { T3_SVID_3COM, T3_SSID_3COM_3C996BT, PHY_BCM5701_PHY_ID, 0 }, + { T3_SVID_3COM, T3_SSID_3COM_3C996SX, 0, 1 }, + { T3_SVID_3COM, T3_SSID_3COM_3C1000T, PHY_BCM5701_PHY_ID, 0 }, + { T3_SVID_3COM, T3_SSID_3COM_3C940BR01, PHY_BCM5701_PHY_ID, 0 }, + + { T3_SVID_DELL, T3_SSID_DELL_VIPER, PHY_BCM5401_PHY_ID, 0 }, + { T3_SVID_DELL, T3_SSID_DELL_JAGUAR, PHY_BCM5401_PHY_ID, 0 }, + { T3_SVID_DELL, T3_SSID_DELL_MERLOT, PHY_BCM5411_PHY_ID, 0 }, + { T3_SVID_DELL, T3_SSID_DELL_SLIM_MERLOT, PHY_BCM5411_PHY_ID, 0 }, + + { T3_SVID_COMPAQ, T3_SSID_COMPAQ_BANSHEE, PHY_BCM5701_PHY_ID, 0 }, + { T3_SVID_COMPAQ, T3_SSID_COMPAQ_BANSHEE_2, PHY_BCM5701_PHY_ID, 0 }, + { T3_SVID_COMPAQ, T3_SSID_COMPAQ_CHANGELING, 0, 1 }, + { T3_SVID_COMPAQ, T3_SSID_COMPAQ_NC7780, PHY_BCM5701_PHY_ID, 0 }, + { T3_SVID_COMPAQ, T3_SSID_COMPAQ_NC7780_2, PHY_BCM5701_PHY_ID, 0 }, + + { 0x1014, 0x0281, 0, 1 }, + }; + LM_UINT32 j; + + for(j = 0; j < sizeof(AdapterArr)/sizeof(LM_ADAPTER_INFO); j++) + { + if(AdapterArr[j].Svid == Svid && AdapterArr[j].Ssid == Ssid) + { + return &AdapterArr[j]; + } + } + + return NULL; +} + + + +/******************************************************************************/ +/* Description: */ +/* This routine sets up receive/transmit buffer descriptions queues. */ +/* */ +/* Return: */ +/* LM_STATUS_SUCCESS */ +/******************************************************************************/ +LM_STATUS +LM_InitializeAdapter( +PLM_DEVICE_BLOCK pDevice) +{ + LM_PHYSICAL_ADDRESS MemPhy; + PLM_UINT8 pMemVirt; + PLM_PACKET pPacket; + LM_STATUS Status; + LM_UINT32 Size; + LM_UINT32 Value32, j; + LM_UINT32 DmaWrCmd, DmaRdCmd, DmaWrBdry, DmaRdBdry; + + MM_ReadConfig32(pDevice, PCI_COMMAND_REG, &Value32); + j = 0; + while (((Value32 & 0x3ff) != (pDevice->PciCommandStatusWords & 0x3ff)) && + (j < 1000)) + { + /* On PCIE devices, there are some rare cases where the device */ + /* is in the process of link-training at this point */ + MM_Wait(200); + MM_WriteConfig32(pDevice, PCI_COMMAND_REG, pDevice->PciCommandStatusWords); + MM_ReadConfig32(pDevice, PCI_COMMAND_REG, &Value32); + j++; + } + MM_WriteConfig32(pDevice, T3_PCI_MISC_HOST_CTRL_REG, pDevice->MiscHostCtrl); + /* Set power state to D0. */ + LM_SetPowerState(pDevice, LM_POWER_STATE_D0); + + /* Intialize the queues. */ + QQ_InitQueue(&pDevice->RxPacketReceivedQ.Container, + MAX_RX_PACKET_DESC_COUNT); + QQ_InitQueue(&pDevice->RxPacketFreeQ.Container, + MAX_RX_PACKET_DESC_COUNT); + + QQ_InitQueue(&pDevice->TxPacketFreeQ.Container,MAX_TX_PACKET_DESC_COUNT); + QQ_InitQueue(&pDevice->TxPacketXmittedQ.Container,MAX_TX_PACKET_DESC_COUNT); + + if(T3_ASIC_5705_OR_5750(pDevice->ChipRevId)) + { + pDevice->RcvRetRcbEntryCount = 512; + pDevice->RcvRetRcbEntryCountMask = 511; + } + else + { + pDevice->RcvRetRcbEntryCount = T3_RCV_RETURN_RCB_ENTRY_COUNT; + pDevice->RcvRetRcbEntryCountMask = T3_RCV_RETURN_RCB_ENTRY_COUNT_MASK; + } + + /* Allocate shared memory for: status block, the buffers for receive */ + /* rings -- standard, mini, jumbo, and return rings. */ + Size = T3_STATUS_BLOCK_SIZE + sizeof(T3_STATS_BLOCK) + + T3_STD_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD) + +#if T3_JUMBO_RCV_RCB_ENTRY_COUNT + T3_JUMBO_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD) + +#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ + (pDevice->RcvRetRcbEntryCount * sizeof(T3_RCV_BD)); + + /* Memory for host based Send BD. */ + if (!(pDevice->Flags & NIC_SEND_BD_FLAG)) + { + Size += sizeof(T3_SND_BD) * T3_SEND_RCB_ENTRY_COUNT; + } + + /* Allocate the memory block. */ + Status = MM_AllocateSharedMemory(pDevice, Size, (PLM_VOID) &pMemVirt, &MemPhy, FALSE); + if(Status != LM_STATUS_SUCCESS) + { + return Status; + } + + DmaWrCmd = DMA_CTRL_WRITE_CMD; + DmaRdCmd = DMA_CTRL_READ_CMD; + DmaWrBdry = DMA_CTRL_WRITE_BOUNDARY_DISABLE; + DmaRdBdry = DMA_CTRL_READ_BOUNDARY_DISABLE; +#ifdef BCM_DISCONNECT_AT_CACHELINE + /* This code is intended for PPC64 and other similar architectures */ + /* Only the following chips support this */ + if ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) || + (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) || + (pDevice->Flags & PCI_EXPRESS_FLAG)) + { + switch(pDevice->CacheLineSize * 4) + { + case 16: + case 32: + case 64: + case 128: + if (!(pDevice->PciState & T3_PCI_STATE_NOT_PCI_X_BUS) && + !(pDevice->Flags & PCI_EXPRESS_FLAG)) + { + /* PCI-X */ + /* use 384 which is a multiple of 16,32,64,128 */ + DmaWrBdry = DMA_CTRL_WRITE_BOUNDARY_384_PCIX; + break; + } + else if (pDevice->Flags & PCI_EXPRESS_FLAG) + { + /* PCI Express */ + /* use 128 which is a multiple of 16,32,64,128 */ + DmaWrCmd = DMA_CTRL_WRITE_BOUNDARY_128_PCIE; + break; + } + /* fall through */ + case 256: + /* use 256 which is a multiple of 16,32,64,128,256 */ + if ((pDevice->PciState & T3_PCI_STATE_NOT_PCI_X_BUS) && + !(pDevice->Flags & PCI_EXPRESS_FLAG)) + { + /* PCI */ + DmaWrBdry = DMA_CTRL_WRITE_BOUNDARY_256; + } + else if (!(pDevice->Flags & PCI_EXPRESS_FLAG)) + { + /* PCI-X */ + DmaWrBdry = DMA_CTRL_WRITE_BOUNDARY_256_PCIX; + } + break; + } + } +#endif + pDevice->DmaReadWriteCtrl = DmaWrCmd | DmaRdCmd | DmaWrBdry | DmaRdBdry; + /* Program DMA Read/Write */ + if (pDevice->Flags & PCI_EXPRESS_FLAG) + { + pDevice->DmaReadWriteCtrl |= 0x001f0000; + } + else if (pDevice->PciState & T3_PCI_STATE_NOT_PCI_X_BUS) + { + if(T3_ASIC_5705_OR_5750(pDevice->ChipRevId)) + { + pDevice->DmaReadWriteCtrl |= 0x003f0000; + } + else + { + pDevice->DmaReadWriteCtrl |= 0x003f000f; + } + } + else + { + if((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703) || + (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704)) + { + /* set bit 23 to enable a PCIX hardware fix */ + pDevice->DmaReadWriteCtrl |= 0x009f0000; + + Value32 = REG_RD(pDevice, PciCfg.ClockCtrl) & 0x1f; + if ((Value32 == 0x6) || (Value32 == 0x7)) + { + pDevice->Flags |= ONE_DMA_AT_ONCE_FLAG; + } + } + else + { + pDevice->DmaReadWriteCtrl |= 0x001b000f; + } + } + if((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703) || + (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704)) + { + pDevice->DmaReadWriteCtrl &= 0xfffffff0; + } + + if (pDevice->Flags & ONE_DMA_AT_ONCE_FLAG) + { + pDevice->DmaReadWriteCtrl |= DMA_CTRL_WRITE_ONE_DMA_AT_ONCE; + } + REG_WR(pDevice, PciCfg.DmaReadWriteCtrl, pDevice->DmaReadWriteCtrl); + + LM_SwitchClocks(pDevice); + + if (LM_DmaTest(pDevice, pMemVirt, MemPhy, 0x400) != LM_STATUS_SUCCESS) + { + return LM_STATUS_FAILURE; + } + + /* Status block. */ + pDevice->pStatusBlkVirt = (PT3_STATUS_BLOCK) pMemVirt; + pDevice->StatusBlkPhy = MemPhy; + pMemVirt += T3_STATUS_BLOCK_SIZE; + LM_INC_PHYSICAL_ADDRESS(&MemPhy, T3_STATUS_BLOCK_SIZE); + + /* Statistics block. */ + pDevice->pStatsBlkVirt = (PT3_STATS_BLOCK) pMemVirt; + pDevice->StatsBlkPhy = MemPhy; + pMemVirt += sizeof(T3_STATS_BLOCK); + LM_INC_PHYSICAL_ADDRESS(&MemPhy, sizeof(T3_STATS_BLOCK)); + + /* Receive standard BD buffer. */ + pDevice->pRxStdBdVirt = (PT3_RCV_BD) pMemVirt; + pDevice->RxStdBdPhy = MemPhy; + + pMemVirt += T3_STD_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD); + LM_INC_PHYSICAL_ADDRESS(&MemPhy, + T3_STD_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD)); + +#if T3_JUMBO_RCV_RCB_ENTRY_COUNT + /* Receive jumbo BD buffer. */ + pDevice->pRxJumboBdVirt = (PT3_RCV_BD) pMemVirt; + pDevice->RxJumboBdPhy = MemPhy; + + pMemVirt += T3_JUMBO_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD); + LM_INC_PHYSICAL_ADDRESS(&MemPhy, + T3_JUMBO_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD)); +#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ + + /* Receive return BD buffer. */ + pDevice->pRcvRetBdVirt = (PT3_RCV_BD) pMemVirt; + pDevice->RcvRetBdPhy = MemPhy; + + pMemVirt += pDevice->RcvRetRcbEntryCount * sizeof(T3_RCV_BD); + LM_INC_PHYSICAL_ADDRESS(&MemPhy, + pDevice->RcvRetRcbEntryCount * sizeof(T3_RCV_BD)); + + /* Set up Send BD. */ + if (!(pDevice->Flags & NIC_SEND_BD_FLAG)) + { + pDevice->pSendBdVirt = (PT3_SND_BD) pMemVirt; + pDevice->SendBdPhy = MemPhy; + + pMemVirt += sizeof(T3_SND_BD) * T3_SEND_RCB_ENTRY_COUNT; + LM_INC_PHYSICAL_ADDRESS(&MemPhy, + sizeof(T3_SND_BD) * T3_SEND_RCB_ENTRY_COUNT); + } +#ifdef BCM_NIC_SEND_BD + else + { + pDevice->pSendBdVirt = (PT3_SND_BD) + pDevice->pMemView->uIntMem.First32k.BufferDesc; + pDevice->SendBdPhy.High = 0; + pDevice->SendBdPhy.Low = T3_NIC_SND_BUFFER_DESC_ADDR; + } +#endif + + /* Allocate memory for packet descriptors. */ + Size = (pDevice->RxPacketDescCnt + + pDevice->TxPacketDescCnt) * MM_PACKET_DESC_SIZE; + Status = MM_AllocateMemory(pDevice, Size, (PLM_VOID *) &pPacket); + if(Status != LM_STATUS_SUCCESS) + { + return Status; + } + pDevice->pPacketDescBase = (PLM_VOID) pPacket; + + /* Create transmit packet descriptors from the memory block and add them */ + /* to the TxPacketFreeQ for each send ring. */ + for(j = 0; j < pDevice->TxPacketDescCnt; j++) + { + /* Ring index. */ + pPacket->Flags = 0; + + /* Queue the descriptor in the TxPacketFreeQ of the 'k' ring. */ + QQ_PushTail(&pDevice->TxPacketFreeQ.Container, pPacket); + + /* Get the pointer to the next descriptor. MM_PACKET_DESC_SIZE */ + /* is the total size of the packet descriptor including the */ + /* os-specific extensions in the UM_PACKET structure. */ + pPacket = (PLM_PACKET) ((PLM_UINT8) pPacket + MM_PACKET_DESC_SIZE); + } /* for(j.. */ + + /* Create receive packet descriptors from the memory block and add them */ + /* to the RxPacketFreeQ. Create the Standard packet descriptors. */ + for(j = 0; j < pDevice->RxStdDescCnt; j++) + { + /* Receive producer ring. */ + pPacket->u.Rx.RcvProdRing = T3_STD_RCV_PROD_RING; + + /* Receive buffer size. */ + pPacket->u.Rx.RxBufferSize = MAX_STD_RCV_BUFFER_SIZE; + + /* Add the descriptor to RxPacketFreeQ. */ + QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket); + + /* Get the pointer to the next descriptor. MM_PACKET_DESC_SIZE */ + /* is the total size of the packet descriptor including the */ + /* os-specific extensions in the UM_PACKET structure. */ + pPacket = (PLM_PACKET) ((PLM_UINT8) pPacket + MM_PACKET_DESC_SIZE); + } /* for */ + +#if T3_JUMBO_RCV_RCB_ENTRY_COUNT + /* Create the Jumbo packet descriptors. */ + for(j = 0; j < pDevice->RxJumboDescCnt; j++) + { + /* Receive producer ring. */ + pPacket->u.Rx.RcvProdRing = T3_JUMBO_RCV_PROD_RING; + + /* Receive buffer size. */ + pPacket->u.Rx.RxBufferSize = pDevice->RxJumboBufferSize; + + /* Add the descriptor to RxPacketFreeQ. */ + QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket); + + /* Get the pointer to the next descriptor. MM_PACKET_DESC_SIZE */ + /* is the total size of the packet descriptor including the */ + /* os-specific extensions in the UM_PACKET structure. */ + pPacket = (PLM_PACKET) ((PLM_UINT8) pPacket + MM_PACKET_DESC_SIZE); + } /* for */ +#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ + + /* Initialize the rest of the packet descriptors. */ + Status = MM_InitializeUmPackets(pDevice); + if(Status != LM_STATUS_SUCCESS) + { + return Status; + } /* if */ + + /* Default receive mask. */ + pDevice->ReceiveMask &= LM_KEEP_VLAN_TAG; + pDevice->ReceiveMask |= LM_ACCEPT_MULTICAST | LM_ACCEPT_BROADCAST | + LM_ACCEPT_UNICAST; + + /* Make sure we are in the first 32k memory window or NicSendBd. */ + REG_WR(pDevice, PciCfg.MemWindowBaseAddr, 0); + + /* Initialize the hardware. */ + Status = LM_ResetAdapter(pDevice); + if(Status != LM_STATUS_SUCCESS) + { + return Status; + } + + /* We are done with initialization. */ + pDevice->InitDone = TRUE; + + return LM_STATUS_SUCCESS; +} /* LM_InitializeAdapter */ + + +LM_STATUS +LM_DisableChip(PLM_DEVICE_BLOCK pDevice) +{ + LM_UINT32 data; + + pDevice->RxMode &= ~RX_MODE_ENABLE; + REG_WR(pDevice, MacCtrl.RxMode, pDevice->RxMode); + if(!(REG_RD(pDevice, MacCtrl.RxMode) & RX_MODE_ENABLE)) + { + MM_Wait(20); + } + data = REG_RD(pDevice, RcvBdIn.Mode); + data &= ~RCV_BD_IN_MODE_ENABLE; + REG_WR(pDevice, RcvBdIn.Mode,data); + if(!(REG_RD(pDevice, RcvBdIn.Mode) & RCV_BD_IN_MODE_ENABLE)) + { + MM_Wait(20); + } + data = REG_RD(pDevice, RcvListPlmt.Mode); + data &= ~RCV_LIST_PLMT_MODE_ENABLE; + REG_WR(pDevice, RcvListPlmt.Mode,data); + if(!(REG_RD(pDevice, RcvListPlmt.Mode) & RCV_LIST_PLMT_MODE_ENABLE)) + { + MM_Wait(20); + } + if(!T3_ASIC_5705_OR_5750(pDevice->ChipRevId)) + { + data = REG_RD(pDevice, RcvListSel.Mode); + data &= ~RCV_LIST_SEL_MODE_ENABLE; + REG_WR(pDevice, RcvListSel.Mode,data); + if(!(REG_RD(pDevice, RcvListSel.Mode) & RCV_LIST_SEL_MODE_ENABLE)) + { + MM_Wait(20); + } + } + data = REG_RD(pDevice, RcvDataBdIn.Mode); + data &= ~RCV_DATA_BD_IN_MODE_ENABLE; + REG_WR(pDevice, RcvDataBdIn.Mode,data); + if(!(REG_RD(pDevice, RcvDataBdIn.Mode) & RCV_DATA_BD_IN_MODE_ENABLE)) + { + MM_Wait(20); + } + data = REG_RD(pDevice, RcvDataComp.Mode); + data &= ~RCV_DATA_COMP_MODE_ENABLE; + REG_WR(pDevice, RcvDataComp.Mode,data); + if(!(REG_RD(pDevice, RcvDataBdIn.Mode) & RCV_DATA_COMP_MODE_ENABLE)) + { + MM_Wait(20); + } + data = REG_RD(pDevice, RcvBdComp.Mode); + data &= ~RCV_BD_COMP_MODE_ENABLE; + REG_WR(pDevice, RcvBdComp.Mode,data); + if(!(REG_RD(pDevice, RcvBdComp.Mode) & RCV_BD_COMP_MODE_ENABLE)) + { + MM_Wait(20); + } + data = REG_RD(pDevice, SndBdSel.Mode); + data &= ~SND_BD_SEL_MODE_ENABLE; + REG_WR(pDevice, SndBdSel.Mode, data); + if(!(REG_RD(pDevice, SndBdSel.Mode) & SND_BD_SEL_MODE_ENABLE)) + { + MM_Wait(20); + } + data = REG_RD(pDevice, SndBdIn.Mode); + data &= ~SND_BD_IN_MODE_ENABLE; + REG_WR(pDevice, SndBdIn.Mode, data); + if(!(REG_RD(pDevice, SndBdIn.Mode) & SND_BD_IN_MODE_ENABLE)) + { + MM_Wait(20); + } + data = REG_RD(pDevice, SndDataIn.Mode); + data &= ~T3_SND_DATA_IN_MODE_ENABLE; + REG_WR(pDevice, SndDataIn.Mode,data); + if(!(REG_RD(pDevice, SndDataIn.Mode) & T3_SND_DATA_IN_MODE_ENABLE)) + { + MM_Wait(20); + } + data = REG_RD(pDevice, DmaRead.Mode); + data &= ~DMA_READ_MODE_ENABLE; + REG_WR(pDevice, DmaRead.Mode, data); + if(!(REG_RD(pDevice, DmaRead.Mode) & DMA_READ_MODE_ENABLE)) + { + MM_Wait(20); + } + data = REG_RD(pDevice, SndDataComp.Mode); + data &= ~SND_DATA_COMP_MODE_ENABLE; + REG_WR(pDevice, SndDataComp.Mode, data); + if(!(REG_RD(pDevice, SndDataComp.Mode) & SND_DATA_COMP_MODE_ENABLE)) + { + MM_Wait(20); + } + if(!T3_ASIC_5705_OR_5750(pDevice->ChipRevId)) + { + data = REG_RD(pDevice,DmaComp.Mode); + data &= ~DMA_COMP_MODE_ENABLE; + REG_WR(pDevice, DmaComp.Mode, data); + if(!(REG_RD(pDevice, DmaComp.Mode) & DMA_COMP_MODE_ENABLE)) + { + MM_Wait(20); + } + } + data = REG_RD(pDevice, SndBdComp.Mode); + data &= ~SND_BD_COMP_MODE_ENABLE; + REG_WR(pDevice, SndBdComp.Mode, data); + if(!(REG_RD(pDevice, SndBdComp.Mode) & SND_BD_COMP_MODE_ENABLE)) + { + MM_Wait(20); + } + /* Clear TDE bit */ + pDevice->MacMode &= ~MAC_MODE_ENABLE_TDE; + REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode); + pDevice->TxMode &= ~TX_MODE_ENABLE; + REG_WR(pDevice, MacCtrl.TxMode, pDevice->TxMode); + if(!(REG_RD(pDevice, MacCtrl.TxMode) & TX_MODE_ENABLE)) + { + MM_Wait(20); + } + data = REG_RD(pDevice, HostCoalesce.Mode); + data &= ~HOST_COALESCE_ENABLE; + REG_WR(pDevice, HostCoalesce.Mode, data); + if(!(REG_RD(pDevice, SndBdIn.Mode) & HOST_COALESCE_ENABLE)) + { + MM_Wait(20); + } + data = REG_RD(pDevice, DmaWrite.Mode); + data &= ~DMA_WRITE_MODE_ENABLE; + REG_WR(pDevice, DmaWrite.Mode,data); + if(!(REG_RD(pDevice, DmaWrite.Mode) & DMA_WRITE_MODE_ENABLE)) + { + MM_Wait(20); + } + if(!T3_ASIC_5705_OR_5750(pDevice->ChipRevId)) + { + data = REG_RD(pDevice, MbufClusterFree.Mode); + data &= ~MBUF_CLUSTER_FREE_MODE_ENABLE; + REG_WR(pDevice, MbufClusterFree.Mode,data); + if(!(REG_RD(pDevice, MbufClusterFree.Mode) & MBUF_CLUSTER_FREE_MODE_ENABLE)) + { + MM_Wait(20); + } + } + /* Reset all FTQs */ + REG_WR(pDevice, Ftq.Reset, 0xffffffff); + REG_WR(pDevice, Ftq.Reset, 0x0); + + if(!T3_ASIC_5705_OR_5750(pDevice->ChipRevId)) + { + data = REG_RD(pDevice, BufMgr.Mode); + data &= ~BUFMGR_MODE_ENABLE; + REG_WR(pDevice, BufMgr.Mode,data); + if(!(REG_RD(pDevice, BufMgr.Mode) & BUFMGR_MODE_ENABLE)) + { + MM_Wait(20); + } + data = REG_RD(pDevice, MemArbiter.Mode); + data &= ~T3_MEM_ARBITER_MODE_ENABLE; + REG_WR(pDevice, MemArbiter.Mode, data); + if(!(REG_RD(pDevice, MemArbiter.Mode) & T3_MEM_ARBITER_MODE_ENABLE)) + { + MM_Wait(20); + } + } + return LM_STATUS_SUCCESS; +} + +LM_STATUS +LM_DisableFW(PLM_DEVICE_BLOCK pDevice) +{ +#ifdef BCM_ASF + int j; + LM_UINT32 Value32; + + if (pDevice->AsfFlags & ASF_ENABLED) + { + MEM_WR_OFFSET(pDevice, T3_CMD_MAILBOX, T3_CMD_NICDRV_PAUSE_FW); + Value32 = REG_RD(pDevice, Grc.RxCpuEvent); + REG_WR(pDevice, Grc.RxCpuEvent, Value32 | BIT_14); + for (j = 0; j < 100; j++) + { + Value32 = REG_RD(pDevice, Grc.RxCpuEvent); + if (!(Value32 & BIT_14)) + { + break; + } + MM_Wait(1); + } + } +#endif + return LM_STATUS_SUCCESS; +} + +/******************************************************************************/ +/* Description: */ +/* This function reinitializes the adapter. */ +/* */ +/* Return: */ +/* LM_STATUS_SUCCESS */ +/******************************************************************************/ +LM_STATUS +LM_ResetAdapter( +PLM_DEVICE_BLOCK pDevice) +{ + LM_UINT32 Value32; + LM_UINT32 j, k; + int reset_count = 0; + + /* Disable interrupt. */ + LM_DisableInterrupt(pDevice); + +restart_reset: + LM_DisableFW(pDevice); + + /* May get a spurious interrupt */ + pDevice->pStatusBlkVirt->Status = STATUS_BLOCK_UPDATED; + + LM_WritePreResetSignatures(pDevice, LM_INIT_RESET); + /* Disable transmit and receive DMA engines. Abort all pending requests. */ + if(pDevice->InitDone) + { + LM_Abort(pDevice); + } + + pDevice->ShuttingDown = FALSE; + + LM_ResetChip(pDevice); + + LM_WriteLegacySignatures(pDevice, LM_INIT_RESET); + + /* Bug: Athlon fix for B3 silicon only. This bit does not do anything */ + /* in other chip revisions except 5750 */ + if ((pDevice->Flags & DELAY_PCI_GRANT_FLAG) && + !(pDevice->Flags & PCI_EXPRESS_FLAG)) + { + REG_WR(pDevice, PciCfg.ClockCtrl, pDevice->ClockCtrl | BIT_31); + } + + if(pDevice->ChipRevId == T3_CHIP_ID_5704_A0) + { + if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE)) + { + Value32 = REG_RD(pDevice, PciCfg.PciState); + Value32 |= T3_PCI_STATE_RETRY_SAME_DMA; + REG_WR(pDevice, PciCfg.PciState, Value32); + } + } + if (T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5704_BX) + { + /* New bits defined in register 0x64 to enable some h/w fixes */ + /* These new bits are 'write-only' */ + Value32 = REG_RD(pDevice, PciCfg.MsiData); + REG_WR(pDevice, PciCfg.MsiData, Value32 | BIT_26 | BIT_28 | BIT_29); + } + + /* Enable TaggedStatus mode. */ + if (pDevice->Flags & USE_TAGGED_STATUS_FLAG) + { + pDevice->MiscHostCtrl |= MISC_HOST_CTRL_ENABLE_TAGGED_STATUS_MODE; + } + + /* Restore PCI configuration registers. */ + MM_WriteConfig32(pDevice, PCI_CACHE_LINE_SIZE_REG, + pDevice->SavedCacheLineReg); +// LM_RegWrInd(pDevice, PCI_SUBSYSTEM_VENDOR_ID_REG, +// (pDevice->SubsystemId << 16) | pDevice->SubsystemVendorId); + MM_WriteConfig32(pDevice, PCI_SUBSYSTEM_VENDOR_ID_REG, + (pDevice->SubsystemId << 16) | pDevice->SubsystemVendorId); + + /* Initialize the statistis Block */ + pDevice->pStatusBlkVirt->Status = 0; + pDevice->pStatusBlkVirt->RcvStdConIdx = 0; + pDevice->pStatusBlkVirt->RcvJumboConIdx = 0; + pDevice->pStatusBlkVirt->RcvMiniConIdx = 0; + + for(j = 0; j < 16; j++) + { + pDevice->pStatusBlkVirt->Idx[j].RcvProdIdx = 0; + pDevice->pStatusBlkVirt->Idx[j].SendConIdx = 0; + } + + for(k = 0; k < T3_STD_RCV_RCB_ENTRY_COUNT ;k++) + { + pDevice->pRxStdBdVirt[k].HostAddr.High = 0; + pDevice->pRxStdBdVirt[k].HostAddr.Low = 0; + pDevice->pRxStdBdVirt[k].Flags = RCV_BD_FLAG_END; + pDevice->pRxStdBdVirt[k].Len = MAX_STD_RCV_BUFFER_SIZE; + } + +#if T3_JUMBO_RCV_RCB_ENTRY_COUNT + /* Receive jumbo BD buffer. */ + for(k = 0; k < T3_JUMBO_RCV_RCB_ENTRY_COUNT; k++) + { + pDevice->pRxJumboBdVirt[k].HostAddr.High = 0; + pDevice->pRxJumboBdVirt[k].HostAddr.Low = 0; + pDevice->pRxJumboBdVirt[k].Flags = RCV_BD_FLAG_END | + RCV_BD_FLAG_JUMBO_RING; + pDevice->pRxJumboBdVirt[k].Len = (LM_UINT16) pDevice->RxJumboBufferSize; + } +#endif + + REG_WR(pDevice, PciCfg.DmaReadWriteCtrl, pDevice->DmaReadWriteCtrl); + + /* GRC mode control register. */ + Value32 = +#ifdef BIG_ENDIAN_HOST + GRC_MODE_BYTE_SWAP_NON_FRAME_DATA | + GRC_MODE_WORD_SWAP_NON_FRAME_DATA | + GRC_MODE_BYTE_SWAP_DATA | + GRC_MODE_WORD_SWAP_DATA | +#else + GRC_MODE_WORD_SWAP_NON_FRAME_DATA | + GRC_MODE_BYTE_SWAP_DATA | + GRC_MODE_WORD_SWAP_DATA | +#endif + GRC_MODE_INT_ON_MAC_ATTN | + GRC_MODE_HOST_STACK_UP; + + /* Configure send BD mode. */ + if (!(pDevice->Flags & NIC_SEND_BD_FLAG)) + { + Value32 |= GRC_MODE_HOST_SEND_BDS; + } +#ifdef BCM_NIC_SEND_BD + else + { + Value32 |= GRC_MODE_4X_NIC_BASED_SEND_RINGS; + } +#endif + + /* Configure pseudo checksum mode. */ + if (pDevice->Flags & NO_TX_PSEUDO_HDR_CSUM_FLAG) + { + Value32 |= GRC_MODE_TX_NO_PSEUDO_HEADER_CHKSUM; + } + + if (pDevice->Flags & NO_RX_PSEUDO_HDR_CSUM_FLAG) + { + Value32 |= GRC_MODE_RX_NO_PSEUDO_HEADER_CHKSUM; + } + + pDevice->GrcMode = Value32; + REG_WR(pDevice, Grc.Mode, Value32); + + /* Setup the timer prescalar register. */ + Value32 = REG_RD(pDevice, Grc.MiscCfg) & ~0xff; + /* Clock is always 66Mhz. */ + REG_WR(pDevice, Grc.MiscCfg, Value32 | (65 << 1)); + + /* Set up the MBUF pool base address and size. */ + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5705) + { +#if INCLUDE_TCP_SEG_SUPPORT + if (pDevice->TaskToOffload & LM_TASK_OFFLOAD_TCP_SEGMENTATION) + { + Value32 = LM_GetStkOffLdFirmwareSize(pDevice); + Value32 = (Value32 + 0x7f) & ~0x7f; + pDevice->MbufBase = T3_NIC_BCM5705_MBUF_POOL_ADDR + Value32; + pDevice->MbufSize = T3_NIC_BCM5705_MBUF_POOL_SIZE - Value32 - 0xa00; + REG_WR(pDevice, BufMgr.MbufPoolAddr, pDevice->MbufBase); + REG_WR(pDevice, BufMgr.MbufPoolSize, pDevice->MbufSize); + } +#endif + } + else if (T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5750) + { + REG_WR(pDevice, BufMgr.MbufPoolAddr, pDevice->MbufBase); + REG_WR(pDevice, BufMgr.MbufPoolSize, pDevice->MbufSize); + + /* Set up the DMA descriptor pool base address and size. */ + REG_WR(pDevice, BufMgr.DmaDescPoolAddr, T3_NIC_DMA_DESC_POOL_ADDR); + REG_WR(pDevice, BufMgr.DmaDescPoolSize, T3_NIC_DMA_DESC_POOL_SIZE); + + } + + /* Configure MBUF and Threshold watermarks */ + /* Configure the DMA read MBUF low water mark. */ + if(pDevice->TxMtu < MAX_ETHERNET_PACKET_BUFFER_SIZE) + { + if(T3_ASIC_5705_OR_5750(pDevice->ChipRevId)) + { + REG_WR(pDevice, BufMgr.MbufReadDmaLowWaterMark, + T3_DEF_DMA_MBUF_LOW_WMARK_5705); + REG_WR(pDevice, BufMgr.MbufMacRxLowWaterMark, + T3_DEF_RX_MAC_MBUF_LOW_WMARK_5705); + REG_WR(pDevice, BufMgr.MbufHighWaterMark, + T3_DEF_MBUF_HIGH_WMARK_5705); + } + else + { + REG_WR(pDevice, BufMgr.MbufReadDmaLowWaterMark, + T3_DEF_DMA_MBUF_LOW_WMARK); + REG_WR(pDevice, BufMgr.MbufMacRxLowWaterMark, + T3_DEF_RX_MAC_MBUF_LOW_WMARK); + REG_WR(pDevice, BufMgr.MbufHighWaterMark, + T3_DEF_MBUF_HIGH_WMARK); + } + } + else + { + REG_WR(pDevice, BufMgr.MbufReadDmaLowWaterMark, + T3_DEF_DMA_MBUF_LOW_WMARK_JUMBO); + REG_WR(pDevice, BufMgr.MbufMacRxLowWaterMark, + T3_DEF_RX_MAC_MBUF_LOW_WMARK_JUMBO); + REG_WR(pDevice, BufMgr.MbufHighWaterMark, + T3_DEF_MBUF_HIGH_WMARK_JUMBO); + } + + REG_WR(pDevice, BufMgr.DmaLowWaterMark, T3_DEF_DMA_DESC_LOW_WMARK); + REG_WR(pDevice, BufMgr.DmaHighWaterMark, T3_DEF_DMA_DESC_HIGH_WMARK); + + /* Enable buffer manager. */ + REG_WR(pDevice, BufMgr.Mode, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE); + + for(j = 0 ;j < 2000; j++) + { + if(REG_RD(pDevice, BufMgr.Mode) & BUFMGR_MODE_ENABLE) + break; + MM_Wait(10); + } + + if(j >= 2000) + { + return LM_STATUS_FAILURE; + } + +/* GRC reset will reset FTQ */ +#if 0 + /* Enable the FTQs. */ + REG_WR(pDevice, Ftq.Reset, 0xffffffff); + REG_WR(pDevice, Ftq.Reset, 0); + + /* Wait until FTQ is ready */ + for(j = 0; j < 2000; j++) + { + if(REG_RD(pDevice, Ftq.Reset) == 0) + break; + MM_Wait(10); + } + + if(j >= 2000) + { + return LM_STATUS_FAILURE; + } +#endif + + /* Receive BD Ring replenish threshold. */ + REG_WR(pDevice, RcvBdIn.StdRcvThreshold, pDevice->RxStdDescCnt/8); + + /* Initialize the Standard Receive RCB. */ + REG_WR(pDevice, RcvDataBdIn.StdRcvRcb.HostRingAddr.High, + pDevice->RxStdBdPhy.High); + REG_WR(pDevice, RcvDataBdIn.StdRcvRcb.HostRingAddr.Low, + pDevice->RxStdBdPhy.Low); + REG_WR(pDevice, RcvDataBdIn.StdRcvRcb.NicRingAddr, + (LM_UINT32) T3_NIC_STD_RCV_BUFFER_DESC_ADDR); + + if(T3_ASIC_5705_OR_5750(pDevice->ChipRevId)) + { + REG_WR(pDevice, RcvDataBdIn.StdRcvRcb.u.MaxLen_Flags, + 512 << 16); + } + else + { + REG_WR(pDevice, RcvDataBdIn.StdRcvRcb.u.MaxLen_Flags, + MAX_STD_RCV_BUFFER_SIZE << 16); + + /* Initialize the Jumbo Receive RCB. */ + REG_WR(pDevice, RcvDataBdIn.JumboRcvRcb.u.MaxLen_Flags, + T3_RCB_FLAG_RING_DISABLED); +#if T3_JUMBO_RCV_RCB_ENTRY_COUNT + REG_WR(pDevice, RcvDataBdIn.JumboRcvRcb.HostRingAddr.High, + pDevice->RxJumboBdPhy.High); + REG_WR(pDevice, RcvDataBdIn.JumboRcvRcb.HostRingAddr.Low, + pDevice->RxJumboBdPhy.Low); + REG_WR(pDevice, RcvDataBdIn.JumboRcvRcb.u.MaxLen_Flags, 0); + REG_WR(pDevice, RcvDataBdIn.JumboRcvRcb.NicRingAddr, + (LM_UINT32) T3_NIC_JUMBO_RCV_BUFFER_DESC_ADDR); + + REG_WR(pDevice, RcvBdIn.JumboRcvThreshold, pDevice->RxJumboDescCnt/8); + +#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ + + /* Initialize the Mini Receive RCB. */ + REG_WR(pDevice, RcvDataBdIn.MiniRcvRcb.u.MaxLen_Flags, + T3_RCB_FLAG_RING_DISABLED); + + /* Disable all the unused rings. */ + for(j = 0; j < T3_MAX_SEND_RCB_COUNT; j++) { + MEM_WR(pDevice, SendRcb[j].u.MaxLen_Flags, + T3_RCB_FLAG_RING_DISABLED); + } /* for */ + + } + + /* Initialize the indices. */ + pDevice->SendProdIdx = 0; + pDevice->SendConIdx = 0; + + MB_REG_WR(pDevice, Mailbox.SendHostProdIdx[0].Low, 0); + MB_REG_RD(pDevice, Mailbox.SendHostProdIdx[0].Low); + MB_REG_WR(pDevice, Mailbox.SendNicProdIdx[0].Low, 0); + MB_REG_RD(pDevice, Mailbox.SendNicProdIdx[0].Low); + + /* Set up host or NIC based send RCB. */ + if (!(pDevice->Flags & NIC_SEND_BD_FLAG)) + { + MEM_WR(pDevice, SendRcb[0].HostRingAddr.High, + pDevice->SendBdPhy.High); + MEM_WR(pDevice, SendRcb[0].HostRingAddr.Low, + pDevice->SendBdPhy.Low); + + /* Setup the RCB. */ + MEM_WR(pDevice, SendRcb[0].u.MaxLen_Flags, + T3_SEND_RCB_ENTRY_COUNT << 16); + + if(!T3_ASIC_5705_OR_5750(pDevice->ChipRevId)) + { + /* Set up the NIC ring address in the RCB. */ + MEM_WR(pDevice, SendRcb[0].NicRingAddr,T3_NIC_SND_BUFFER_DESC_ADDR); + } + for(k = 0; k < T3_SEND_RCB_ENTRY_COUNT; k++) + { + pDevice->pSendBdVirt[k].HostAddr.High = 0; + pDevice->pSendBdVirt[k].HostAddr.Low = 0; + } + } +#ifdef BCM_NIC_SEND_BD + else + { + MEM_WR(pDevice, SendRcb[0].HostRingAddr.High, 0); + MEM_WR(pDevice, SendRcb[0].HostRingAddr.Low, 0); + MEM_WR(pDevice, SendRcb[0].NicRingAddr, + pDevice->SendBdPhy.Low); + + for(k = 0; k < T3_SEND_RCB_ENTRY_COUNT; k++) + { + MM_MEMWRITEL(&(pDevice->pSendBdVirt[k].HostAddr.High), 0); + MM_MEMWRITEL(&(pDevice->pSendBdVirt[k].HostAddr.Low), 0); + MM_MEMWRITEL(&(pDevice->pSendBdVirt[k].u1.Len_Flags), 0); + pDevice->ShadowSendBd[k].HostAddr.High = 0; + pDevice->ShadowSendBd[k].u1.Len_Flags = 0; + } + } +#endif + MM_ATOMIC_SET(&pDevice->SendBdLeft, T3_SEND_RCB_ENTRY_COUNT-1); + + /* Configure the receive return rings. */ + for(j = 0; j < T3_MAX_RCV_RETURN_RCB_COUNT; j++) + { + MEM_WR(pDevice, RcvRetRcb[j].u.MaxLen_Flags, T3_RCB_FLAG_RING_DISABLED); + } + + pDevice->RcvRetConIdx = 0; + + MEM_WR(pDevice, RcvRetRcb[0].HostRingAddr.High, + pDevice->RcvRetBdPhy.High); + MEM_WR(pDevice, RcvRetRcb[0].HostRingAddr.Low, + pDevice->RcvRetBdPhy.Low); + + MEM_WR(pDevice, RcvRetRcb[0].NicRingAddr, 0); + + /* Setup the RCB. */ + MEM_WR(pDevice, RcvRetRcb[0].u.MaxLen_Flags, + pDevice->RcvRetRcbEntryCount << 16); + + /* Reinitialize RX ring producer index */ + MB_REG_WR(pDevice, Mailbox.RcvStdProdIdx.Low, 0); + MB_REG_RD(pDevice, Mailbox.RcvStdProdIdx.Low); + MB_REG_WR(pDevice, Mailbox.RcvJumboProdIdx.Low, 0); + MB_REG_RD(pDevice, Mailbox.RcvJumboProdIdx.Low); + MB_REG_WR(pDevice, Mailbox.RcvMiniProdIdx.Low, 0); + MB_REG_RD(pDevice, Mailbox.RcvMiniProdIdx.Low); + +#if T3_JUMBO_RCV_RCB_ENTRY_COUNT + pDevice->RxJumboProdIdx = 0; + pDevice->RxJumboQueuedCnt = 0; +#endif + + /* Reinitialize our copy of the indices. */ + pDevice->RxStdProdIdx = 0; + pDevice->RxStdQueuedCnt = 0; + +#if T3_JUMBO_RCV_ENTRY_COUNT + pDevice->RxJumboProdIdx = 0; +#endif /* T3_JUMBO_RCV_ENTRY_COUNT */ + + /* Configure the MAC address. */ + LM_SetMacAddress(pDevice, pDevice->NodeAddress); + + /* Initialize the transmit random backoff seed. */ + Value32 = (pDevice->NodeAddress[0] + pDevice->NodeAddress[1] + + pDevice->NodeAddress[2] + pDevice->NodeAddress[3] + + pDevice->NodeAddress[4] + pDevice->NodeAddress[5]) & + MAC_TX_BACKOFF_SEED_MASK; + REG_WR(pDevice, MacCtrl.TxBackoffSeed, Value32); + + /* Receive MTU. Frames larger than the MTU is marked as oversized. */ + REG_WR(pDevice, MacCtrl.MtuSize, pDevice->RxMtu + 8); /* CRC + VLAN. */ + + /* Configure Time slot/IPG per 802.3 */ + REG_WR(pDevice, MacCtrl.TxLengths, 0x2620); + + /* + * Configure Receive Rules so that packets don't match + * Programmble rule will be queued to Return Ring 1 + */ + REG_WR(pDevice, MacCtrl.RcvRuleCfg, RX_RULE_DEFAULT_CLASS); + + /* + * Configure to have 16 Classes of Services (COS) and one + * queue per class. Bad frames are queued to RRR#1. + * And frames don't match rules are also queued to COS#1. + */ + REG_WR(pDevice, RcvListPlmt.Config, 0x181); + + /* Enable Receive Placement Statistics */ + if ((pDevice->DmaReadFifoSize == DMA_READ_MODE_FIFO_LONG_BURST) && + (pDevice->TaskToOffload & LM_TASK_OFFLOAD_TCP_SEGMENTATION)) + { + Value32 = REG_RD(pDevice, RcvListPlmt.StatsEnableMask); + Value32 &= ~T3_DISABLE_LONG_BURST_READ_DYN_FIX; + REG_WR(pDevice, RcvListPlmt.StatsEnableMask, Value32); + } + else + { + REG_WR(pDevice, RcvListPlmt.StatsEnableMask,0xffffff); + } + REG_WR(pDevice, RcvListPlmt.StatsCtrl, RCV_LIST_STATS_ENABLE); + + /* Enable Send Data Initator Statistics */ + REG_WR(pDevice, SndDataIn.StatsEnableMask,0xffffff); + REG_WR(pDevice, SndDataIn.StatsCtrl, + T3_SND_DATA_IN_STATS_CTRL_ENABLE | \ + T3_SND_DATA_IN_STATS_CTRL_FASTER_UPDATE); + + /* Disable the host coalescing state machine before configuring it's */ + /* parameters. */ + REG_WR(pDevice, HostCoalesce.Mode, 0); + for(j = 0; j < 2000; j++) + { + Value32 = REG_RD(pDevice, HostCoalesce.Mode); + if(!(Value32 & HOST_COALESCE_ENABLE)) + { + break; + } + MM_Wait(10); + } + + /* Host coalescing configurations. */ + REG_WR(pDevice, HostCoalesce.RxCoalescingTicks, pDevice->RxCoalescingTicks); + REG_WR(pDevice, HostCoalesce.TxCoalescingTicks, pDevice->TxCoalescingTicks); + REG_WR(pDevice, HostCoalesce.RxMaxCoalescedFrames, + pDevice->RxMaxCoalescedFrames); + REG_WR(pDevice, HostCoalesce.TxMaxCoalescedFrames, + pDevice->TxMaxCoalescedFrames); + if(!T3_ASIC_5705_OR_5750(pDevice->ChipRevId)) + { + REG_WR(pDevice, HostCoalesce.RxCoalescedTickDuringInt, + pDevice->RxCoalescingTicksDuringInt); + REG_WR(pDevice, HostCoalesce.TxCoalescedTickDuringInt, + pDevice->TxCoalescingTicksDuringInt); + } + REG_WR(pDevice, HostCoalesce.RxMaxCoalescedFramesDuringInt, + pDevice->RxMaxCoalescedFramesDuringInt); + REG_WR(pDevice, HostCoalesce.TxMaxCoalescedFramesDuringInt, + pDevice->TxMaxCoalescedFramesDuringInt); + + /* Initialize the address of the status block. The NIC will DMA */ + /* the status block to this memory which resides on the host. */ + REG_WR(pDevice, HostCoalesce.StatusBlkHostAddr.High, + pDevice->StatusBlkPhy.High); + REG_WR(pDevice, HostCoalesce.StatusBlkHostAddr.Low, + pDevice->StatusBlkPhy.Low); + + /* Initialize the address of the statistics block. The NIC will DMA */ + /* the statistics to this block of memory. */ + if(!T3_ASIC_5705_OR_5750(pDevice->ChipRevId)) + { + REG_WR(pDevice, HostCoalesce.StatsBlkHostAddr.High, + pDevice->StatsBlkPhy.High); + REG_WR(pDevice, HostCoalesce.StatsBlkHostAddr.Low, + pDevice->StatsBlkPhy.Low); + + REG_WR(pDevice, HostCoalesce.StatsCoalescingTicks, + pDevice->StatsCoalescingTicks); + + REG_WR(pDevice, HostCoalesce.StatsBlkNicAddr, 0x300); + REG_WR(pDevice, HostCoalesce.StatusBlkNicAddr,0xb00); + } + + /* Enable Host Coalesing state machine */ + REG_WR(pDevice, HostCoalesce.Mode, HOST_COALESCE_ENABLE | + pDevice->CoalesceMode); + + /* Enable the Receive BD Completion state machine. */ + REG_WR(pDevice, RcvBdComp.Mode, RCV_BD_COMP_MODE_ENABLE | + RCV_BD_COMP_MODE_ATTN_ENABLE); + + /* Enable the Receive List Placement state machine. */ + REG_WR(pDevice, RcvListPlmt.Mode, RCV_LIST_PLMT_MODE_ENABLE); + + if(!T3_ASIC_5705_OR_5750(pDevice->ChipRevId)) + { + /* Enable the Receive List Selector state machine. */ + REG_WR(pDevice, RcvListSel.Mode, RCV_LIST_SEL_MODE_ENABLE | + RCV_LIST_SEL_MODE_ATTN_ENABLE); + } + + /* Clear the statistics block. */ + for(j = 0x0300; j < 0x0b00; j = j + 4) + { + MEM_WR_OFFSET(pDevice, j, 0); + } + + /* Enable transmit DMA, clear statistics. */ + pDevice->MacMode = MAC_MODE_ENABLE_TX_STATISTICS | + MAC_MODE_ENABLE_RX_STATISTICS | MAC_MODE_ENABLE_TDE | + MAC_MODE_ENABLE_RDE | MAC_MODE_ENABLE_FHDE; + REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode | + MAC_MODE_CLEAR_RX_STATISTICS | MAC_MODE_CLEAR_TX_STATISTICS); + + /* GRC miscellaneous local control register. */ + pDevice->GrcLocalCtrl = GRC_MISC_LOCAL_CTRL_INT_ON_ATTN | + GRC_MISC_LOCAL_CTRL_AUTO_SEEPROM; + + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) + { + pDevice->GrcLocalCtrl |= GRC_MISC_LOCAL_CTRL_GPIO_OE1 | + GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1; + } + else if ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704) && + !(pDevice->Flags & EEPROM_WP_FLAG)) + { + /* Make sure we're on Vmain */ + /* The other port may cause us to be on Vaux */ + pDevice->GrcLocalCtrl |= GRC_MISC_LOCAL_CTRL_GPIO_OE2 | + GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2; + } + + RAW_REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl); + MM_Wait(40); + + /* Reset RX counters. */ + for(j = 0; j < sizeof(LM_RX_COUNTERS); j++) + { + ((PLM_UINT8) &pDevice->RxCounters)[j] = 0; + } + + /* Reset TX counters. */ + for(j = 0; j < sizeof(LM_TX_COUNTERS); j++) + { + ((PLM_UINT8) &pDevice->TxCounters)[j] = 0; + } + + MB_REG_WR(pDevice, Mailbox.Interrupt[0].Low, 0); + MB_REG_RD(pDevice, Mailbox.Interrupt[0].Low); + pDevice->LastTag = 0; + + if(!T3_ASIC_5705_OR_5750(pDevice->ChipRevId)) + { + /* Enable the DMA Completion state machine. */ + REG_WR(pDevice, DmaComp.Mode, DMA_COMP_MODE_ENABLE); + } + + /* Enable the DMA Write state machine. */ + Value32 = DMA_WRITE_MODE_ENABLE | + DMA_WRITE_MODE_TARGET_ABORT_ATTN_ENABLE | + DMA_WRITE_MODE_MASTER_ABORT_ATTN_ENABLE | + DMA_WRITE_MODE_PARITY_ERROR_ATTN_ENABLE | + DMA_WRITE_MODE_ADDR_OVERFLOW_ATTN_ENABLE | + DMA_WRITE_MODE_FIFO_OVERRUN_ATTN_ENABLE | + DMA_WRITE_MODE_FIFO_UNDERRUN_ATTN_ENABLE | + DMA_WRITE_MODE_FIFO_OVERREAD_ATTN_ENABLE | + DMA_WRITE_MODE_LONG_READ_ATTN_ENABLE; + + if (pDevice->Flags & DMA_WR_MODE_RX_ACCELERATE_FLAG) + { + Value32 |= DMA_WRITE_MODE_RECEIVE_ACCELERATE; + } + REG_WR(pDevice, DmaWrite.Mode, Value32); + + if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE)) + { + if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703) + { + Value32 = REG_RD(pDevice, PciCfg.PciXCapabilities); + Value32 &= ~PCIX_CMD_MAX_BURST_MASK; + Value32 |= PCIX_CMD_MAX_BURST_CPIOB << PCIX_CMD_MAX_BURST_SHL; + REG_WR(pDevice, PciCfg.PciXCapabilities, Value32); + } + else if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704) + { + Value32 = REG_RD(pDevice, PciCfg.PciXCapabilities); + Value32 &= ~(PCIX_CMD_MAX_SPLIT_MASK | PCIX_CMD_MAX_BURST_MASK); + Value32 |= ((PCIX_CMD_MAX_BURST_CPIOB << PCIX_CMD_MAX_BURST_SHL) & + PCIX_CMD_MAX_BURST_MASK); + if (pDevice->Flags & MULTI_SPLIT_ENABLE_FLAG) + { + Value32 |= (pDevice->SplitModeMaxReq << PCIX_CMD_MAX_SPLIT_SHL) + & PCIX_CMD_MAX_SPLIT_MASK; + } + REG_WR(pDevice, PciCfg.PciXCapabilities, Value32); + } + } + + /* Enable the Read DMA state machine. */ + Value32 = DMA_READ_MODE_ENABLE | + DMA_READ_MODE_TARGET_ABORT_ATTN_ENABLE | + DMA_READ_MODE_MASTER_ABORT_ATTN_ENABLE | + DMA_READ_MODE_PARITY_ERROR_ATTN_ENABLE | + DMA_READ_MODE_ADDR_OVERFLOW_ATTN_ENABLE | + DMA_READ_MODE_FIFO_OVERRUN_ATTN_ENABLE | + DMA_READ_MODE_FIFO_UNDERRUN_ATTN_ENABLE | + DMA_READ_MODE_FIFO_OVERREAD_ATTN_ENABLE | + DMA_READ_MODE_LONG_READ_ATTN_ENABLE; + + if (pDevice->Flags & MULTI_SPLIT_ENABLE_FLAG) + { + Value32 |= DMA_READ_MODE_MULTI_SPLIT_ENABLE; + } + + if (T3_ASIC_5705_OR_5750(pDevice->ChipRevId)) + { + Value32 |= pDevice->DmaReadFifoSize; + } +#if INCLUDE_TCP_SEG_SUPPORT + if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5750) + { + Value32 |= BIT_27; + } +#endif + + + REG_WR(pDevice, DmaRead.Mode, Value32); + + /* Enable the Receive Data Completion state machine. */ + REG_WR(pDevice, RcvDataComp.Mode, RCV_DATA_COMP_MODE_ENABLE | + RCV_DATA_COMP_MODE_ATTN_ENABLE); + + if (!T3_ASIC_5705_OR_5750(pDevice->ChipRevId)) + { + /* Enable the Mbuf Cluster Free state machine. */ + REG_WR(pDevice, MbufClusterFree.Mode, MBUF_CLUSTER_FREE_MODE_ENABLE); + } + + /* Enable the Send Data Completion state machine. */ + REG_WR(pDevice, SndDataComp.Mode, SND_DATA_COMP_MODE_ENABLE); + + /* Enable the Send BD Completion state machine. */ + REG_WR(pDevice, SndBdComp.Mode, SND_BD_COMP_MODE_ENABLE | + SND_BD_COMP_MODE_ATTN_ENABLE); + + /* Enable the Receive BD Initiator state machine. */ + REG_WR(pDevice, RcvBdIn.Mode, RCV_BD_IN_MODE_ENABLE | + RCV_BD_IN_MODE_BD_IN_DIABLED_RCB_ATTN_ENABLE); + + /* Enable the Receive Data and Receive BD Initiator state machine. */ + REG_WR(pDevice, RcvDataBdIn.Mode, RCV_DATA_BD_IN_MODE_ENABLE | + RCV_DATA_BD_IN_MODE_INVALID_RING_SIZE); + + /* Enable the Send Data Initiator state machine. */ + REG_WR(pDevice, SndDataIn.Mode, T3_SND_DATA_IN_MODE_ENABLE); + +#if INCLUDE_TCP_SEG_SUPPORT + if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5750) + { + REG_WR(pDevice, SndDataIn.Mode, T3_SND_DATA_IN_MODE_ENABLE | 0x8); + } +#endif + + /* Enable the Send BD Initiator state machine. */ + REG_WR(pDevice, SndBdIn.Mode, SND_BD_IN_MODE_ENABLE | + SND_BD_IN_MODE_ATTN_ENABLE); + + /* Enable the Send BD Selector state machine. */ + REG_WR(pDevice, SndBdSel.Mode, SND_BD_SEL_MODE_ENABLE | + SND_BD_SEL_MODE_ATTN_ENABLE); + +#if INCLUDE_5701_AX_FIX + /* Load the firmware for the 5701_A0 workaround. */ + if(pDevice->ChipRevId == T3_CHIP_ID_5701_A0) + { + LM_LoadRlsFirmware(pDevice); + } +#endif + + /* Queue Rx packet buffers. */ + if(pDevice->QueueRxPackets) + { + LM_QueueRxPackets(pDevice); + } + + if (pDevice->ChipRevId == T3_CHIP_ID_5705_A0) + { + Value32 = MEM_RD_OFFSET(pDevice, T3_NIC_STD_RCV_BUFFER_DESC_ADDR + 8); + j = 0; + while ((Value32 != MAX_STD_RCV_BUFFER_SIZE) && (j < 10)) + { + MM_Wait(20); + Value32 = MEM_RD_OFFSET(pDevice, T3_NIC_STD_RCV_BUFFER_DESC_ADDR + 8); + j++; + } + if (j >= 10) + { + reset_count++; + LM_Abort(pDevice); + if (reset_count > 5) + return LM_STATUS_FAILURE; + goto restart_reset; + } + } + + /* Enable the transmitter. */ + pDevice->TxMode = TX_MODE_ENABLE; + REG_WR(pDevice, MacCtrl.TxMode, pDevice->TxMode); + + /* Enable the receiver. */ + pDevice->RxMode = (pDevice->RxMode & RX_MODE_KEEP_VLAN_TAG) | + RX_MODE_ENABLE; + REG_WR(pDevice, MacCtrl.RxMode, pDevice->RxMode); + +#ifdef BCM_WOL + if (pDevice->RestoreOnWakeUp) + { + pDevice->RestoreOnWakeUp = FALSE; + pDevice->DisableAutoNeg = pDevice->WakeUpDisableAutoNeg; + pDevice->RequestedLineSpeed = pDevice->WakeUpRequestedLineSpeed; + pDevice->RequestedDuplexMode = pDevice->WakeUpRequestedDuplexMode; + } +#endif + + /* Disable auto polling. */ + pDevice->MiMode = 0xc0000; + REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode); + + REG_WR(pDevice, MacCtrl.LedCtrl, pDevice->LedCtrl); + + /* Activate Link to enable MAC state machine */ + REG_WR(pDevice, MacCtrl.MiStatus, MI_STATUS_ENABLE_LINK_STATUS_ATTN); + + if (pDevice->TbiFlags & ENABLE_TBI_FLAG) + { + REG_WR(pDevice, MacCtrl.RxMode, RX_MODE_RESET); + REG_RD_BACK(pDevice, MacCtrl.RxMode); + MM_Wait(10); + REG_WR(pDevice, MacCtrl.RxMode, pDevice->RxMode); + if (pDevice->ChipRevId == T3_CHIP_ID_5703_A1) + { + REG_WR(pDevice, MacCtrl.SerdesCfg, 0x616000); + } + if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704) + { + /* Set SerDes drive transmission level to 1.2V */ + Value32 = REG_RD(pDevice, MacCtrl.SerdesCfg) & 0xfffff000; + REG_WR(pDevice, MacCtrl.SerdesCfg, Value32 | 0x880); + } + } + + REG_WR(pDevice, MacCtrl.LowWaterMarkMaxRxFrame, 2); + + if (!pDevice->InitDone) + { + pDevice->LinkStatus = LM_STATUS_LINK_DOWN; + } + + if (!(pDevice->TbiFlags & ENABLE_TBI_FLAG) && + ((pDevice->PhyId & PHY_ID_MASK) != PHY_BCM5401_PHY_ID)) + { + /* 5401 PHY needs a delay of about 1 second after PHY reset */ + /* Without the delay, it has problem linking at forced 10 half */ + /* So skip the reset... */ + LM_ResetPhy(pDevice); + } + + /* Setup the phy chip. */ + LM_SetupPhy(pDevice); + + if (!(pDevice->TbiFlags & ENABLE_TBI_FLAG)) { + /* Clear CRC stats */ + LM_ReadPhy(pDevice, 0x1e, &Value32); + LM_WritePhy(pDevice, 0x1e, Value32 | 0x8000); + LM_ReadPhy(pDevice, 0x14, &Value32); + } + + /* Set up the receive mask. */ + LM_SetReceiveMask(pDevice, pDevice->ReceiveMask); + +#if INCLUDE_TCP_SEG_SUPPORT + if (pDevice->TaskToOffload & LM_TASK_OFFLOAD_TCP_SEGMENTATION) + { + if (LM_LoadStkOffLdFirmware(pDevice) == LM_STATUS_FAILURE) + { + return LM_STATUS_FAILURE; + } + } +#endif + LM_WritePostResetSignatures(pDevice, LM_INIT_RESET); + + return LM_STATUS_SUCCESS; +} /* LM_ResetAdapter */ + + +/******************************************************************************/ +/* Description: */ +/* This routine disables the adapter from generating interrupts. */ +/* */ +/* Return: */ +/* LM_STATUS_SUCCESS */ +/******************************************************************************/ +LM_STATUS +LM_DisableInterrupt( + PLM_DEVICE_BLOCK pDevice) +{ + REG_WR(pDevice, PciCfg.MiscHostCtrl, pDevice->MiscHostCtrl | + MISC_HOST_CTRL_MASK_PCI_INT); + MB_REG_WR(pDevice, Mailbox.Interrupt[0].Low, 1); + if (pDevice->Flags & FLUSH_POSTED_WRITE_FLAG) + { + MB_REG_RD(pDevice, Mailbox.Interrupt[0].Low); + } + + return LM_STATUS_SUCCESS; +} + + + +/******************************************************************************/ +/* Description: */ +/* This routine enables the adapter to generate interrupts. */ +/* */ +/* Return: */ +/* LM_STATUS_SUCCESS */ +/******************************************************************************/ +LM_STATUS +LM_EnableInterrupt( + PLM_DEVICE_BLOCK pDevice) +{ + MB_REG_WR(pDevice, Mailbox.Interrupt[0].Low, pDevice->LastTag << 24); + if (pDevice->Flags & FLUSH_POSTED_WRITE_FLAG) + { + MB_REG_RD(pDevice, Mailbox.Interrupt[0].Low); + } + + REG_WR(pDevice, PciCfg.MiscHostCtrl, pDevice->MiscHostCtrl & + ~MISC_HOST_CTRL_MASK_PCI_INT); + + REG_WR(pDevice, HostCoalesce.Mode, pDevice->CoalesceMode | + HOST_COALESCE_ENABLE | HOST_COALESCE_NOW); + + return LM_STATUS_SUCCESS; +} + + + +/******************************************************************************/ +/* Description: */ +/* This routine puts a packet on the wire if there is a transmit DMA */ +/* descriptor available; otherwise the packet is queued for later */ +/* transmission. If the second argue is NULL, this routine will put */ +/* the queued packet on the wire if possible. */ +/* */ +/* Return: */ +/* LM_STATUS_SUCCESS */ +/******************************************************************************/ +LM_STATUS +LM_SendPacket(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket) +{ + LM_UINT32 FragCount; + PT3_SND_BD pSendBd, pTmpSendBd; +#ifdef BCM_NIC_SEND_BD + PT3_SND_BD pShadowSendBd; + T3_SND_BD NicSendBdArr[MAX_FRAGMENT_COUNT]; +#endif + LM_UINT32 StartIdx, Idx; + + while (1) + { + /* Initalize the send buffer descriptors. */ + StartIdx = Idx = pDevice->SendProdIdx; + +#ifdef BCM_NIC_SEND_BD + if (pDevice->Flags & NIC_SEND_BD_FLAG) + { + pTmpSendBd = pSendBd = &NicSendBdArr[0]; + } + else +#endif + { + pTmpSendBd = pSendBd = &pDevice->pSendBdVirt[Idx]; + } + + /* Next producer index. */ + for(FragCount = 0; ; ) + { + LM_UINT32 Value32, Len; + + /* Initialize the pointer to the send buffer fragment. */ + MM_MapTxDma(pDevice, pPacket, &pSendBd->HostAddr, &Len, FragCount); + + pSendBd->u2.VlanTag = pPacket->VlanTag; + + /* Setup the control flags and send buffer size. */ + Value32 = (Len << 16) | pPacket->Flags; + +#if INCLUDE_TCP_SEG_SUPPORT + if (Value32 & (SND_BD_FLAG_CPU_PRE_DMA | SND_BD_FLAG_CPU_POST_DMA)) + { + if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5750) + { + pSendBd->u2.s2.Reserved = pPacket->u.Tx.MaxSegmentSize; + } + else if (FragCount == 0) + { + pSendBd->u2.s2.Reserved = pPacket->u.Tx.MaxSegmentSize; + } + else + { + pSendBd->u2.s2.Reserved = 0; + Value32 &= 0xffff0fff; + } + } +#endif + Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK; + + FragCount++; + if (FragCount >= pPacket->u.Tx.FragCount) + { + pSendBd->u1.Len_Flags = Value32 | SND_BD_FLAG_END; + break; + } + else + { + pSendBd->u1.Len_Flags = Value32; + } + + pSendBd++; + if ((Idx == 0) && + !(pDevice->Flags & NIC_SEND_BD_FLAG)) + { + pSendBd = &pDevice->pSendBdVirt[0]; + } + + pDevice->SendRing[Idx] = 0; + + } /* for */ + if (pDevice->Flags & TX_4G_WORKAROUND_FLAG) + { + if (LM_Test4GBoundary(pDevice, pPacket, pTmpSendBd) == + LM_STATUS_SUCCESS) + { + if (MM_CoalesceTxBuffer(pDevice, pPacket) != LM_STATUS_SUCCESS) + { + QQ_PushHead(&pDevice->TxPacketFreeQ.Container, pPacket); + return LM_STATUS_FAILURE; + } + continue; + } + } + break; + } + /* Put the packet descriptor in the ActiveQ. */ + pDevice->SendRing[StartIdx] = pPacket; + +#ifdef BCM_NIC_SEND_BD + if (pDevice->Flags & NIC_SEND_BD_FLAG) + { + pSendBd = &pDevice->pSendBdVirt[StartIdx]; + pShadowSendBd = &pDevice->ShadowSendBd[StartIdx]; + + while (StartIdx != Idx) + { + LM_UINT32 Value32; + + if ((Value32 = pTmpSendBd->HostAddr.High) != + pShadowSendBd->HostAddr.High) + { + MM_MEMWRITEL(&(pSendBd->HostAddr.High), Value32); + pShadowSendBd->HostAddr.High = Value32; + } + + MM_MEMWRITEL(&(pSendBd->HostAddr.Low), pTmpSendBd->HostAddr.Low); + + if ((Value32 = pTmpSendBd->u1.Len_Flags) != + pShadowSendBd->u1.Len_Flags) + { + MM_MEMWRITEL(&(pSendBd->u1.Len_Flags), Value32); + pShadowSendBd->u1.Len_Flags = Value32; + } + + if (pPacket->Flags & SND_BD_FLAG_VLAN_TAG) + { + MM_MEMWRITEL(&(pSendBd->u2.VlanTag), pTmpSendBd->u2.VlanTag); + } + + StartIdx = (StartIdx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK; + if (StartIdx == 0) + { + pSendBd = &pDevice->pSendBdVirt[0]; + pShadowSendBd = &pDevice->ShadowSendBd[0]; + } + else + { + pSendBd++; + pShadowSendBd++; + } + pTmpSendBd++; + } + MM_WMB(); + MB_REG_WR(pDevice, Mailbox.SendNicProdIdx[0].Low, Idx); + + if(T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5700_BX) + { + MB_REG_WR(pDevice, Mailbox.SendNicProdIdx[0].Low, Idx); + } + if (pDevice->Flags & FLUSH_POSTED_WRITE_FLAG) + { + MB_REG_RD(pDevice, Mailbox.SendNicProdIdx[0].Low); + } + } + else +#endif + { + MM_WMB(); + MB_REG_WR(pDevice, Mailbox.SendHostProdIdx[0].Low, Idx); + + if(T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5700_BX) + { + MB_REG_WR(pDevice, Mailbox.SendHostProdIdx[0].Low, Idx); + } + if (pDevice->Flags & FLUSH_POSTED_WRITE_FLAG) + { + MB_REG_RD(pDevice, Mailbox.SendHostProdIdx[0].Low); + } + } + + /* Update the SendBdLeft count. */ + MM_ATOMIC_SUB(&pDevice->SendBdLeft, pPacket->u.Tx.FragCount); + + /* Update the producer index. */ + pDevice->SendProdIdx = Idx; + + return LM_STATUS_SUCCESS; +} + +STATIC LM_STATUS +LM_Test4GBoundary(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket, + PT3_SND_BD pSendBd) +{ + int FragCount; + LM_UINT32 Idx, Base, Len; + + Idx = pDevice->SendProdIdx; + for(FragCount = 0; ; ) + { + Len = pSendBd->u1.Len_Flags >> 16; + if (((Base = pSendBd->HostAddr.Low) > 0xffffdcc0) && + ((Base + 8 + Len) < Base)) + { + return LM_STATUS_SUCCESS; + } + FragCount++; + if (FragCount >= pPacket->u.Tx.FragCount) + { + break; + } + pSendBd++; + if (!(pDevice->Flags & NIC_SEND_BD_FLAG)) + { + Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK; + if (Idx == 0) + { + pSendBd = &pDevice->pSendBdVirt[0]; + } + } + } + return LM_STATUS_FAILURE; +} + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +LM_UINT32 +ComputeCrc32(LM_UINT8 *pBuffer, LM_UINT32 BufferSize) +{ + LM_UINT32 Reg; + LM_UINT32 Tmp; + int j, k; + + Reg = 0xffffffff; + + for(j = 0; j < BufferSize; j++) + { + Reg ^= pBuffer[j]; + + for(k = 0; k < 8; k++) + { + Tmp = Reg & 0x01; + + Reg >>= 1; + + if(Tmp) + { + Reg ^= 0xedb88320; + } + } + } + + return ~Reg; +} /* ComputeCrc32 */ + + + +/******************************************************************************/ +/* Description: */ +/* This routine sets the receive control register according to ReceiveMask */ +/* */ +/* Return: */ +/* LM_STATUS_SUCCESS */ +/******************************************************************************/ +LM_STATUS +LM_SetReceiveMask(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Mask) +{ + LM_UINT32 ReceiveMask; + LM_UINT32 RxMode; + LM_UINT32 j, k; + + ReceiveMask = Mask; + + RxMode = pDevice->RxMode; + + if(Mask & LM_ACCEPT_UNICAST) + { + Mask &= ~LM_ACCEPT_UNICAST; + } + + if(Mask & LM_ACCEPT_MULTICAST) + { + Mask &= ~LM_ACCEPT_MULTICAST; + } + + if(Mask & LM_ACCEPT_ALL_MULTICAST) + { + Mask &= ~LM_ACCEPT_ALL_MULTICAST; + } + + if(Mask & LM_ACCEPT_BROADCAST) + { + Mask &= ~LM_ACCEPT_BROADCAST; + } + + RxMode &= ~RX_MODE_KEEP_VLAN_TAG; + if (Mask & LM_KEEP_VLAN_TAG) + { + RxMode |= RX_MODE_KEEP_VLAN_TAG; + Mask &= ~LM_KEEP_VLAN_TAG; + } + + RxMode &= ~RX_MODE_PROMISCUOUS_MODE; + if(Mask & LM_PROMISCUOUS_MODE) + { + RxMode |= RX_MODE_PROMISCUOUS_MODE; + Mask &= ~LM_PROMISCUOUS_MODE; + } + + RxMode &= ~(RX_MODE_ACCEPT_RUNTS | RX_MODE_ACCEPT_OVERSIZED); + if(Mask & LM_ACCEPT_ERROR_PACKET) + { + RxMode |= RX_MODE_ACCEPT_RUNTS | RX_MODE_ACCEPT_OVERSIZED; + Mask &= ~LM_ACCEPT_ERROR_PACKET; + } + + /* Make sure all the bits are valid before committing changes. */ + if(Mask) + { + return LM_STATUS_FAILURE; + } + + /* Commit the new filter. */ + pDevice->ReceiveMask = ReceiveMask; + + pDevice->RxMode = RxMode; + + if (pDevice->PowerLevel != LM_POWER_STATE_D0) + { + return LM_STATUS_SUCCESS; + } + + REG_WR(pDevice, MacCtrl.RxMode, RxMode); + + /* Set up the MC hash table. */ + if(ReceiveMask & LM_ACCEPT_ALL_MULTICAST) + { + for(k = 0; k < 4; k++) + { + REG_WR(pDevice, MacCtrl.HashReg[k], 0xffffffff); + } + } + else if(ReceiveMask & LM_ACCEPT_MULTICAST) + { + for(k = 0; k < 4; k++) + { + REG_WR(pDevice, MacCtrl.HashReg[k], pDevice->MulticastHash[k]); + } + } + else + { + /* Reject all multicast frames. */ + for(j = 0; j < 4; j++) + { + REG_WR(pDevice, MacCtrl.HashReg[j], 0); + } + } + + /* By default, Tigon3 will accept broadcast frames. We need to setup */ + if(ReceiveMask & LM_ACCEPT_BROADCAST) + { + REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Rule, + REJECT_BROADCAST_RULE1_RULE & RCV_DISABLE_RULE_MASK); + REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Value, + REJECT_BROADCAST_RULE1_VALUE & RCV_DISABLE_RULE_MASK); + REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Rule, + REJECT_BROADCAST_RULE1_RULE & RCV_DISABLE_RULE_MASK); + REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Value, + REJECT_BROADCAST_RULE1_VALUE & RCV_DISABLE_RULE_MASK); + } + else + { + REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Rule, + REJECT_BROADCAST_RULE1_RULE); + REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Value, + REJECT_BROADCAST_RULE1_VALUE); + REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Rule, + REJECT_BROADCAST_RULE2_RULE); + REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Value, + REJECT_BROADCAST_RULE2_VALUE); + } + + if (!T3_ASIC_5705_OR_5750(pDevice->ChipRevId)) + { + k = 16; + } + else + { + k = 8; + } +#ifdef BCM_ASF + if (pDevice->AsfFlags & ASF_ENABLED) + { + k -= 4; + } +#endif + + /* disable the rest of the rules. */ + for(j = RCV_LAST_RULE_IDX; j < k; j++) + { + REG_WR(pDevice, MacCtrl.RcvRules[j].Rule, 0); + REG_WR(pDevice, MacCtrl.RcvRules[j].Value, 0); + } + + return LM_STATUS_SUCCESS; +} /* LM_SetReceiveMask */ + + + +/******************************************************************************/ +/* Description: */ +/* Disable the interrupt and put the transmitter and receiver engines in */ +/* an idle state. Also aborts all pending send requests and receive */ +/* buffers. */ +/* */ +/* Return: */ +/* LM_STATUS_SUCCESS */ +/******************************************************************************/ +LM_STATUS +LM_Abort( +PLM_DEVICE_BLOCK pDevice) +{ + PLM_PACKET pPacket; + LM_UINT Idx; + + LM_DisableInterrupt(pDevice); + + LM_DisableChip(pDevice); + + /* Abort packets that have already queued to go out. */ + Idx = pDevice->SendConIdx; + for ( ; ; ) + { + if ((pPacket = pDevice->SendRing[Idx])) + { + pDevice->SendRing[Idx] = 0; + pPacket->PacketStatus = LM_STATUS_TRANSMIT_ABORTED; + pDevice->TxCounters.TxPacketAbortedCnt++; + + MM_ATOMIC_ADD(&pDevice->SendBdLeft, pPacket->u.Tx.FragCount); + Idx = (Idx + pPacket->u.Tx.FragCount) & + T3_SEND_RCB_ENTRY_COUNT_MASK; + + QQ_PushTail(&pDevice->TxPacketXmittedQ.Container, pPacket); + } + else + { + break; + } + } + + /* Cleanup the receive return rings. */ +#ifdef BCM_NAPI_RXPOLL + LM_ServiceRxPoll(pDevice, T3_RCV_RETURN_RCB_ENTRY_COUNT); +#else + LM_ServiceRxInterrupt(pDevice); +#endif + + /* Indicate packets to the protocol. */ + MM_IndicateTxPackets(pDevice); + +#ifdef BCM_NAPI_RXPOLL + + /* Move the receive packet descriptors in the ReceivedQ to the */ + /* free queue. */ + for(; ;) + { + pPacket = (PLM_PACKET) QQ_PopHead( + &pDevice->RxPacketReceivedQ.Container); + if(pPacket == NULL) + { + break; + } + MM_UnmapRxDma(pDevice, pPacket); + QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket); + } +#else + /* Indicate received packets to the protocols. */ + MM_IndicateRxPackets(pDevice); +#endif + + /* Clean up the Std Receive Producer ring. */ + /* Don't always trust the consumer idx in the status block in case of */ + /* hw failure */ + Idx = 0; + + while(Idx < T3_STD_RCV_RCB_ENTRY_COUNT) + { + if ((pPacket = pDevice->RxStdRing[Idx])) + { + MM_UnmapRxDma(pDevice, pPacket); + QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket); + pDevice->RxStdRing[Idx] = 0; + } + + Idx++; + } /* while */ + + /* Reinitialize our copy of the indices. */ + pDevice->RxStdProdIdx = 0; + +#if T3_JUMBO_RCV_RCB_ENTRY_COUNT + /* Clean up the Jumbo Receive Producer ring. */ + Idx = 0; + + while(Idx < T3_JUMBO_RCV_RCB_ENTRY_COUNT) + { + if ((pPacket = pDevice->RxJumboRing[Idx])) + { + MM_UnmapRxDma(pDevice, pPacket); + QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket); + pDevice->RxJumboRing[Idx] = 0; + } + Idx++; + } /* while */ + + /* Reinitialize our copy of the indices. */ + pDevice->RxJumboProdIdx = 0; +#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ + + /* Initialize the statistis Block */ + pDevice->pStatusBlkVirt->Status = 0; + pDevice->pStatusBlkVirt->RcvStdConIdx = 0; + pDevice->pStatusBlkVirt->RcvJumboConIdx = 0; + pDevice->pStatusBlkVirt->RcvMiniConIdx = 0; + + return LM_STATUS_SUCCESS; +} /* LM_Abort */ + + + +/******************************************************************************/ +/* Description: */ +/* Disable the interrupt and put the transmitter and receiver engines in */ +/* an idle state. Aborts all pending send requests and receive buffers. */ +/* Also free all the receive buffers. */ +/* */ +/* Return: */ +/* LM_STATUS_SUCCESS */ +/******************************************************************************/ +LM_STATUS +LM_DoHalt(LM_DEVICE_BLOCK *pDevice) +{ + PLM_PACKET pPacket; + LM_UINT32 EntryCnt; + + LM_DisableFW(pDevice); + + LM_WritePreResetSignatures(pDevice, LM_SHUTDOWN_RESET); + LM_Abort(pDevice); + + /* Get the number of entries in the queue. */ + EntryCnt = QQ_GetEntryCnt(&pDevice->RxPacketFreeQ.Container); + + /* Make sure all the packets have been accounted for. */ + for(EntryCnt = 0; EntryCnt < pDevice->RxPacketDescCnt; EntryCnt++) + { + pPacket = (PLM_PACKET) QQ_PopHead(&pDevice->RxPacketFreeQ.Container); + if (pPacket == 0) + break; + + MM_FreeRxBuffer(pDevice, pPacket); + + QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket); + } + + LM_ResetChip(pDevice); + LM_WriteLegacySignatures(pDevice, LM_SHUTDOWN_RESET); + + /* Restore PCI configuration registers. */ + MM_WriteConfig32(pDevice, PCI_CACHE_LINE_SIZE_REG, + pDevice->SavedCacheLineReg); + LM_RegWrInd(pDevice, PCI_SUBSYSTEM_VENDOR_ID_REG, + (pDevice->SubsystemId << 16) | pDevice->SubsystemVendorId); + + /* Reprogram the MAC address. */ + LM_SetMacAddress(pDevice, pDevice->NodeAddress); + + return LM_STATUS_SUCCESS; +} /* LM_DoHalt */ + + +LM_STATUS +LM_Halt(LM_DEVICE_BLOCK *pDevice) +{ + LM_STATUS status; + + status = LM_DoHalt(pDevice); + LM_WritePostResetSignatures(pDevice, LM_SHUTDOWN_RESET); + return status; +} + + +STATIC LM_VOID +LM_WritePreResetSignatures(LM_DEVICE_BLOCK *pDevice, LM_RESET_TYPE Mode) +{ + MEM_WR_OFFSET(pDevice, T3_FIRMWARE_MAILBOX,T3_MAGIC_NUM_FIRMWARE_INIT_DONE); +#ifdef BCM_ASF + if (pDevice->AsfFlags & ASF_NEW_HANDSHAKE) + { + if (Mode == LM_INIT_RESET) + { + MEM_WR_OFFSET(pDevice, T3_DRV_STATE_MAILBOX, T3_DRV_STATE_START); + } + else if (Mode == LM_SHUTDOWN_RESET) + { + MEM_WR_OFFSET(pDevice, T3_DRV_STATE_MAILBOX, T3_DRV_STATE_UNLOAD); + } + else if (Mode == LM_SUSPEND_RESET) + { + MEM_WR_OFFSET(pDevice, T3_DRV_STATE_MAILBOX, T3_DRV_STATE_SUSPEND); + } + } +#endif +} + +STATIC LM_VOID +LM_WritePostResetSignatures(LM_DEVICE_BLOCK *pDevice, LM_RESET_TYPE Mode) +{ +#ifdef BCM_ASF + if (pDevice->AsfFlags & ASF_NEW_HANDSHAKE) + { + if (Mode == LM_INIT_RESET) + { + MEM_WR_OFFSET(pDevice, T3_DRV_STATE_MAILBOX, + T3_DRV_STATE_START_DONE); + } + else if (Mode == LM_SHUTDOWN_RESET) + { + MEM_WR_OFFSET(pDevice, T3_DRV_STATE_MAILBOX, + T3_DRV_STATE_UNLOAD_DONE); + } + } +#endif +} + +STATIC LM_VOID +LM_WriteLegacySignatures(LM_DEVICE_BLOCK *pDevice, LM_RESET_TYPE Mode) +{ +#ifdef BCM_ASF + if (pDevice->AsfFlags & ASF_ENABLED) + { + if (Mode == LM_INIT_RESET) + { + MEM_WR_OFFSET(pDevice, T3_DRV_STATE_MAILBOX, T3_DRV_STATE_START); + } + else if (Mode == LM_SHUTDOWN_RESET) + { + MEM_WR_OFFSET(pDevice, T3_DRV_STATE_MAILBOX, T3_DRV_STATE_UNLOAD); + } + else if (Mode == LM_SUSPEND_RESET) + { + MEM_WR_OFFSET(pDevice, T3_DRV_STATE_MAILBOX, T3_DRV_STATE_SUSPEND); + } + } +#endif +} + +STATIC LM_STATUS +LM_ResetChip(PLM_DEVICE_BLOCK pDevice) +{ + LM_UINT32 Value32; + LM_UINT32 j, MaxWait; + + /* Wait for access to the nvram interface before resetting. This is */ + /* a workaround to prevent EEPROM corruption. */ + if(T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700 && + T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5701) + { + /* Request access to the flash interface. */ + LM_NvramGetLock(pDevice); + } + + Value32 = GRC_MISC_CFG_CORE_CLOCK_RESET; + if (pDevice->Flags & PCI_EXPRESS_FLAG) + { + if (REG_RD_OFFSET(pDevice, 0x7e2c) == 0x60) /* PCIE 1.0 system */ + { + REG_WR_OFFSET(pDevice, 0x7e2c, 0x20); + } + if (pDevice->ChipRevId != T3_CHIP_ID_5750_A0) + { + /* This bit prevents PCIE link training during GRC reset */ + REG_WR(pDevice, Grc.MiscCfg, BIT_29); /* Write bit 29 first */ + Value32 |= BIT_29; /* and keep bit 29 set during GRC reset */ + } + } + if (T3_ASIC_5705_OR_5750(pDevice->ChipRevId)) + { + Value32 |= GRC_MISC_GPHY_KEEP_POWER_DURING_RESET; + } + /* Global reset. */ + RAW_REG_WR(pDevice, Grc.MiscCfg, Value32); + MM_Wait(40); MM_Wait(40); MM_Wait(40); + +#ifdef INCLUDE_5750_A0_FIX + if (pDevice->Flags & PCI_EXPRESS_FLAG) + { + if (pDevice->ChipRevId == T3_CHIP_ID_5750_A0) + { + /* 500 msec wait for link training to complete */ + for (j = 0; j < 5000; j++) + { + MM_Wait(100); + } + MM_ReadConfig32(pDevice, 0xc4, &Value32); + MM_WriteConfig32(pDevice, 0xc4, Value32 | BIT_15); + } + /* Set PCIE max payload size and clear error status */ + MM_WriteConfig32(pDevice, 0xd8, 0xf5000); + } +#endif + + /* make sure we re-enable indirect accesses */ + MM_WriteConfig32(pDevice, T3_PCI_MISC_HOST_CTRL_REG, + pDevice->MiscHostCtrl); + + /* Set MAX PCI retry to zero. */ + Value32 = T3_PCI_STATE_PCI_ROM_ENABLE | T3_PCI_STATE_PCI_ROM_RETRY_ENABLE; + if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0) + { + if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE)) + { + Value32 |= T3_PCI_STATE_RETRY_SAME_DMA; + } + } + MM_WriteConfig32(pDevice, T3_PCI_STATE_REG, Value32); + + /* Restore PCI command register. */ + MM_WriteConfig32(pDevice, PCI_COMMAND_REG, + pDevice->PciCommandStatusWords); + + /* Disable PCI-X relaxed ordering bit. */ + MM_ReadConfig32(pDevice, PCIX_CAP_REG, &Value32); + Value32 &= ~PCIX_ENABLE_RELAXED_ORDERING; + MM_WriteConfig32(pDevice, PCIX_CAP_REG, Value32); + + /* Enable memory arbiter. */ + REG_WR(pDevice, MemArbiter.Mode, T3_MEM_ARBITER_MODE_ENABLE); + + if (pDevice->ChipRevId == T3_CHIP_ID_5750_A3) + { + /* Because of chip bug on A3, we need to kill the CPU */ + LM_DisableFW(pDevice); + REG_WR_OFFSET(pDevice, 0x5000, 0x400); + } +#ifdef BIG_ENDIAN_HOST + /* Reconfigure the mode register. */ + Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA | + GRC_MODE_WORD_SWAP_NON_FRAME_DATA | + GRC_MODE_BYTE_SWAP_DATA | + GRC_MODE_WORD_SWAP_DATA; +#else + /* Reconfigure the mode register. */ + Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA | GRC_MODE_BYTE_SWAP_DATA; +#endif + REG_WR(pDevice, Grc.Mode, Value32); + +#ifdef INCLUDE_5750_A0_FIX + if (pDevice->ChipRevId == T3_CHIP_ID_5750_A0) + { + Value32 = REG_RD_OFFSET(pDevice, 0xc4); + REG_WR_OFFSET(pDevice, 0xc4, Value32 | BIT_15); + } +#endif + if ((pDevice->Flags & MINI_PCI_FLAG) && + (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5705)) + { + pDevice->ClockCtrl |= T3_PCI_CLKRUN_OUTPUT_EN; + if (pDevice->ChipRevId == T3_CHIP_ID_5705_A0) + { + pDevice->ClockCtrl |= T3_PCI_FORCE_CLKRUN; + } + REG_WR(pDevice, PciCfg.ClockCtrl, pDevice->ClockCtrl); + } + + if (pDevice->TbiFlags & ENABLE_TBI_FLAG) { + pDevice->MacMode = MAC_MODE_PORT_MODE_TBI; + REG_WR(pDevice, MacCtrl.Mode, MAC_MODE_PORT_MODE_TBI); + } + else { + REG_WR(pDevice, MacCtrl.Mode, 0); + } + + /* Wait for the firmware to finish initialization. */ + if (pDevice->Flags & FLASH_DETECTED_FLAG) + { + MaxWait = 1000; + } + else + { + MaxWait = 10000; + } + for(j = 0; j < MaxWait; j++) + { + MM_Wait(100); + + if (j < 50) + continue; + + Value32 = MEM_RD_OFFSET(pDevice, T3_FIRMWARE_MAILBOX); + if(Value32 == ~T3_MAGIC_NUM_FIRMWARE_INIT_DONE) + { + break; + } + } + if ((j >= MaxWait) && (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704)) + { + /* workaround - need to reset nvram of both devices at the same time */ + /* if the boot code is not running */ + if (LM_NvramGetLock(pDevice) != LM_STATUS_SUCCESS) + { + LM_DEVICE_BLOCK *pDevice2; + + REG_WR(pDevice, Nvram.Cmd, NVRAM_CMD_RESET); + pDevice2 = MM_FindPeerDev(pDevice); + if (pDevice2 && !pDevice2->InitDone) + { + REG_WR(pDevice2, Nvram.Cmd, NVRAM_CMD_RESET); + } + } + else + { + LM_NvramReleaseLock(pDevice); + } + } + + if ((pDevice->Flags & PCI_EXPRESS_FLAG) && + (pDevice->ChipRevId != T3_CHIP_ID_5750_A0)) + { + /* Enable PCIE bug fix */ + Value32 = REG_RD_OFFSET(pDevice, 0x7c00); + REG_WR_OFFSET(pDevice, 0x7c00, Value32 | BIT_25); + } +#ifdef BCM_ASF + pDevice->AsfFlags = 0; + Value32 = MEM_RD_OFFSET(pDevice, T3_NIC_DATA_SIG_ADDR); + if (Value32 == T3_NIC_DATA_SIG) + { + Value32 = MEM_RD_OFFSET(pDevice, T3_NIC_DATA_NIC_CFG_ADDR); + if (Value32 & T3_NIC_CFG_ENABLE_ASF) + { + pDevice->AsfFlags = ASF_ENABLED; + if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5750) + { + pDevice->AsfFlags |= ASF_NEW_HANDSHAKE; + } + } + } +#endif + + return LM_STATUS_SUCCESS; +} + + +LM_STATUS +LM_ShutdownChip(PLM_DEVICE_BLOCK pDevice, LM_RESET_TYPE Mode) +{ + LM_DisableFW(pDevice); + LM_WritePreResetSignatures(pDevice, Mode); + if (pDevice->InitDone) + { + LM_Abort(pDevice); + } + else + { + LM_DisableChip(pDevice); + } + LM_ResetChip(pDevice); + LM_WriteLegacySignatures(pDevice, Mode); + LM_WritePostResetSignatures(pDevice, Mode); + return LM_STATUS_SUCCESS; +} + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +void +LM_ServiceTxInterrupt( +PLM_DEVICE_BLOCK pDevice) { + PLM_PACKET pPacket; + LM_UINT32 HwConIdx; + LM_UINT32 SwConIdx; + + HwConIdx = pDevice->pStatusBlkVirt->Idx[0].SendConIdx; + + /* Get our copy of the consumer index. The buffer descriptors */ + /* that are in between the consumer indices are freed. */ + SwConIdx = pDevice->SendConIdx; + + /* Move the packets from the TxPacketActiveQ that are sent out to */ + /* the TxPacketXmittedQ. Packets that are sent use the */ + /* descriptors that are between SwConIdx and HwConIdx. */ + while(SwConIdx != HwConIdx) + { + pPacket = pDevice->SendRing[SwConIdx]; + pDevice->SendRing[SwConIdx] = 0; + + /* Set the return status. */ + pPacket->PacketStatus = LM_STATUS_SUCCESS; + + /* Put the packet in the TxPacketXmittedQ for indication later. */ + QQ_PushTail(&pDevice->TxPacketXmittedQ.Container, pPacket); + + /* Move to the next packet's BD. */ + SwConIdx = (SwConIdx + pPacket->u.Tx.FragCount) & + T3_SEND_RCB_ENTRY_COUNT_MASK; + + /* Update the number of unused BDs. */ + MM_ATOMIC_ADD(&pDevice->SendBdLeft, pPacket->u.Tx.FragCount); + + /* Get the new updated HwConIdx. */ + HwConIdx = pDevice->pStatusBlkVirt->Idx[0].SendConIdx; + } /* while */ + + /* Save the new SwConIdx. */ + pDevice->SendConIdx = SwConIdx; + +} /* LM_ServiceTxInterrupt */ + + +#ifdef BCM_NAPI_RXPOLL +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +int +LM_ServiceRxPoll(PLM_DEVICE_BLOCK pDevice, int limit) +{ + PLM_PACKET pPacket; + PT3_RCV_BD pRcvBd; + LM_UINT32 HwRcvRetProdIdx; + LM_UINT32 SwRcvRetConIdx; + int received = 0; + + /* Loop thru the receive return rings for received packets. */ + HwRcvRetProdIdx = pDevice->pStatusBlkVirt->Idx[0].RcvProdIdx; + + SwRcvRetConIdx = pDevice->RcvRetConIdx; + MM_RMB(); + while (SwRcvRetConIdx != HwRcvRetProdIdx) + { + pRcvBd = &pDevice->pRcvRetBdVirt[SwRcvRetConIdx]; + + /* Get the received packet descriptor. */ + pPacket = (PLM_PACKET) (MM_UINT_PTR(pDevice->pPacketDescBase) + + MM_UINT_PTR(pRcvBd->Opaque)); + + switch(pPacket->u.Rx.RcvProdRing) { +#if T3_JUMBO_RCV_RCB_ENTRY_COUNT + case T3_JUMBO_RCV_PROD_RING: /* Jumbo Receive Ring. */ + pDevice->RxJumboRing[pPacket->u.Rx.RcvRingProdIdx] = 0; + break; +#endif + case T3_STD_RCV_PROD_RING: /* Standard Receive Ring. */ + pDevice->RxStdRing[pPacket->u.Rx.RcvRingProdIdx] = 0; + break; + } + + /* Check the error flag. */ + if(pRcvBd->ErrorFlag && + pRcvBd->ErrorFlag != RCV_BD_ERR_ODD_NIBBLED_RCVD_MII) + { + pPacket->PacketStatus = LM_STATUS_FAILURE; + + pDevice->RxCounters.RxPacketErrCnt++; + + if(pRcvBd->ErrorFlag & RCV_BD_ERR_BAD_CRC) + { + pDevice->RxCounters.RxErrCrcCnt++; + } + + if(pRcvBd->ErrorFlag & RCV_BD_ERR_COLL_DETECT) + { + pDevice->RxCounters.RxErrCollCnt++; + } + + if(pRcvBd->ErrorFlag & RCV_BD_ERR_LINK_LOST_DURING_PKT) + { + pDevice->RxCounters.RxErrLinkLostCnt++; + } + + if(pRcvBd->ErrorFlag & RCV_BD_ERR_PHY_DECODE_ERR) + { + pDevice->RxCounters.RxErrPhyDecodeCnt++; + } + + if(pRcvBd->ErrorFlag & RCV_BD_ERR_ODD_NIBBLED_RCVD_MII) + { + pDevice->RxCounters.RxErrOddNibbleCnt++; + } + + if(pRcvBd->ErrorFlag & RCV_BD_ERR_MAC_ABORT) + { + pDevice->RxCounters.RxErrMacAbortCnt++; + } + + if(pRcvBd->ErrorFlag & RCV_BD_ERR_LEN_LT_64) + { + pDevice->RxCounters.RxErrShortPacketCnt++; + } + + if(pRcvBd->ErrorFlag & RCV_BD_ERR_TRUNC_NO_RESOURCES) + { + pDevice->RxCounters.RxErrNoResourceCnt++; + } + + if(pRcvBd->ErrorFlag & RCV_BD_ERR_GIANT_FRAME_RCVD) + { + pDevice->RxCounters.RxErrLargePacketCnt++; + } + } + else + { + pPacket->PacketStatus = LM_STATUS_SUCCESS; + pPacket->PacketSize = pRcvBd->Len - 4; + + pPacket->Flags = pRcvBd->Flags; + if(pRcvBd->Flags & RCV_BD_FLAG_VLAN_TAG) + { + pPacket->VlanTag = pRcvBd->VlanTag; + } + + pPacket->u.Rx.TcpUdpChecksum = pRcvBd->TcpUdpCksum; + } + + /* Put the packet descriptor containing the received packet */ + /* buffer in the RxPacketReceivedQ for indication later. */ + QQ_PushTail(&pDevice->RxPacketReceivedQ.Container, pPacket); + + /* Go to the next buffer descriptor. */ + SwRcvRetConIdx = (SwRcvRetConIdx + 1) & + pDevice->RcvRetRcbEntryCountMask; + + if (++received >= limit) + { + break; + } + } /* while */ + + pDevice->RcvRetConIdx = SwRcvRetConIdx; + + /* Update the receive return ring consumer index. */ + MB_REG_WR(pDevice, Mailbox.RcvRetConIdx[0].Low, SwRcvRetConIdx); + if (pDevice->Flags & FLUSH_POSTED_WRITE_FLAG) + { + MB_REG_RD(pDevice, Mailbox.RcvRetConIdx[0].Low); + } + return received; +} /* LM_ServiceRxPoll */ +#endif /* BCM_NAPI_RXPOLL */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +void +LM_ServiceRxInterrupt(PLM_DEVICE_BLOCK pDevice) +{ +#ifndef BCM_NAPI_RXPOLL + PLM_PACKET pPacket; + PT3_RCV_BD pRcvBd; +#endif + LM_UINT32 HwRcvRetProdIdx; + LM_UINT32 SwRcvRetConIdx; + + /* Loop thru the receive return rings for received packets. */ + HwRcvRetProdIdx = pDevice->pStatusBlkVirt->Idx[0].RcvProdIdx; + + SwRcvRetConIdx = pDevice->RcvRetConIdx; +#ifdef BCM_NAPI_RXPOLL + if (!pDevice->RxPoll) + { + if (SwRcvRetConIdx != HwRcvRetProdIdx) + { + if (MM_ScheduleRxPoll(pDevice) == LM_STATUS_SUCCESS) + { + pDevice->RxPoll = TRUE; + REG_WR(pDevice, Grc.Mode, + pDevice->GrcMode | GRC_MODE_NO_INTERRUPT_ON_RECEIVE); + } + } + } +#else + MM_RMB(); + while(SwRcvRetConIdx != HwRcvRetProdIdx) + { + pRcvBd = &pDevice->pRcvRetBdVirt[SwRcvRetConIdx]; + + /* Get the received packet descriptor. */ + pPacket = (PLM_PACKET) (MM_UINT_PTR(pDevice->pPacketDescBase) + + MM_UINT_PTR(pRcvBd->Opaque)); + + switch(pPacket->u.Rx.RcvProdRing) { +#if T3_JUMBO_RCV_RCB_ENTRY_COUNT + case T3_JUMBO_RCV_PROD_RING: /* Jumbo Receive Ring. */ + pDevice->RxJumboRing[pPacket->u.Rx.RcvRingProdIdx] = 0; + break; +#endif + case T3_STD_RCV_PROD_RING: /* Standard Receive Ring. */ + pDevice->RxStdRing[pPacket->u.Rx.RcvRingProdIdx] = 0; + break; + } + + /* Check the error flag. */ + if(pRcvBd->ErrorFlag && + pRcvBd->ErrorFlag != RCV_BD_ERR_ODD_NIBBLED_RCVD_MII) + { + pPacket->PacketStatus = LM_STATUS_FAILURE; + + pDevice->RxCounters.RxPacketErrCnt++; + + if(pRcvBd->ErrorFlag & RCV_BD_ERR_BAD_CRC) + { + pDevice->RxCounters.RxErrCrcCnt++; + } + + if(pRcvBd->ErrorFlag & RCV_BD_ERR_COLL_DETECT) + { + pDevice->RxCounters.RxErrCollCnt++; + } + + if(pRcvBd->ErrorFlag & RCV_BD_ERR_LINK_LOST_DURING_PKT) + { + pDevice->RxCounters.RxErrLinkLostCnt++; + } + + if(pRcvBd->ErrorFlag & RCV_BD_ERR_PHY_DECODE_ERR) + { + pDevice->RxCounters.RxErrPhyDecodeCnt++; + } + + if(pRcvBd->ErrorFlag & RCV_BD_ERR_ODD_NIBBLED_RCVD_MII) + { + pDevice->RxCounters.RxErrOddNibbleCnt++; + } + + if(pRcvBd->ErrorFlag & RCV_BD_ERR_MAC_ABORT) + { + pDevice->RxCounters.RxErrMacAbortCnt++; + } + + if(pRcvBd->ErrorFlag & RCV_BD_ERR_LEN_LT_64) + { + pDevice->RxCounters.RxErrShortPacketCnt++; + } + + if(pRcvBd->ErrorFlag & RCV_BD_ERR_TRUNC_NO_RESOURCES) + { + pDevice->RxCounters.RxErrNoResourceCnt++; + } + + if(pRcvBd->ErrorFlag & RCV_BD_ERR_GIANT_FRAME_RCVD) + { + pDevice->RxCounters.RxErrLargePacketCnt++; + } + } + else + { + pPacket->PacketStatus = LM_STATUS_SUCCESS; + pPacket->PacketSize = pRcvBd->Len - 4; + + pPacket->Flags = pRcvBd->Flags; + if(pRcvBd->Flags & RCV_BD_FLAG_VLAN_TAG) + { + pPacket->VlanTag = pRcvBd->VlanTag; + } + + pPacket->u.Rx.TcpUdpChecksum = pRcvBd->TcpUdpCksum; + } + + /* Put the packet descriptor containing the received packet */ + /* buffer in the RxPacketReceivedQ for indication later. */ + QQ_PushTail(&pDevice->RxPacketReceivedQ.Container, pPacket); + + /* Go to the next buffer descriptor. */ + SwRcvRetConIdx = (SwRcvRetConIdx + 1) & + pDevice->RcvRetRcbEntryCountMask; + + } /* while */ + + pDevice->RcvRetConIdx = SwRcvRetConIdx; + + /* Update the receive return ring consumer index. */ + MB_REG_WR(pDevice, Mailbox.RcvRetConIdx[0].Low, SwRcvRetConIdx); + if (pDevice->Flags & FLUSH_POSTED_WRITE_FLAG) + { + MB_REG_RD(pDevice, Mailbox.RcvRetConIdx[0].Low); + } +#endif +} /* LM_ServiceRxInterrupt */ + + + +/******************************************************************************/ +/* Description: */ +/* This is the interrupt event handler routine. It acknowledges all */ +/* pending interrupts and process all pending events. */ +/* */ +/* Return: */ +/* LM_STATUS_SUCCESS */ +/******************************************************************************/ +LM_STATUS +LM_ServiceInterrupts( + PLM_DEVICE_BLOCK pDevice) +{ + LM_UINT32 Value32; + int ServicePhyInt = FALSE; + + /* Setup the phy chip whenever the link status changes. */ + if(pDevice->LinkChngMode == T3_LINK_CHNG_MODE_USE_STATUS_REG) + { + Value32 = REG_RD(pDevice, MacCtrl.Status); + if(pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT) + { + if (Value32 & MAC_STATUS_MI_INTERRUPT) + { + ServicePhyInt = TRUE; + } + } + else if(Value32 & MAC_STATUS_LINK_STATE_CHANGED) + { + ServicePhyInt = TRUE; + } + } + else + { + if(pDevice->pStatusBlkVirt->Status & STATUS_BLOCK_LINK_CHANGED_STATUS) + { + pDevice->pStatusBlkVirt->Status = STATUS_BLOCK_UPDATED | + (pDevice->pStatusBlkVirt->Status & ~STATUS_BLOCK_LINK_CHANGED_STATUS); + ServicePhyInt = TRUE; + } + } +#if INCLUDE_TBI_SUPPORT + if (pDevice->IgnoreTbiLinkChange == TRUE) + { + ServicePhyInt = FALSE; + } +#endif + if (ServicePhyInt == TRUE) + { + MM_ACQUIRE_PHY_LOCK_IN_IRQ(pDevice); + LM_SetupPhy(pDevice); + MM_RELEASE_PHY_LOCK_IN_IRQ(pDevice); + } + + /* Service receive and transmit interrupts. */ + LM_ServiceRxInterrupt(pDevice); + LM_ServiceTxInterrupt(pDevice); + +#ifndef BCM_NAPI_RXPOLL + /* No spinlock for this queue since this routine is serialized. */ + if(!QQ_Empty(&pDevice->RxPacketReceivedQ.Container)) + { + /* Indicate receive packets. */ + MM_IndicateRxPackets(pDevice); +// LM_QueueRxPackets(pDevice); + } +#endif + + /* No spinlock for this queue since this routine is serialized. */ + if(!QQ_Empty(&pDevice->TxPacketXmittedQ.Container)) + { + MM_IndicateTxPackets(pDevice); + } + + return LM_STATUS_SUCCESS; +} /* LM_ServiceInterrupts */ + + +/******************************************************************************/ +/* Description: Add a Multicast address. Note that MC addresses, once added, */ +/* cannot be individually deleted. All addresses must be */ +/* cleared. */ +/* */ +/* Return: */ +/******************************************************************************/ +LM_STATUS +LM_MulticastAdd(LM_DEVICE_BLOCK *pDevice, PLM_UINT8 pMcAddress) +{ + + LM_UINT32 RegIndex; + LM_UINT32 Bitpos; + LM_UINT32 Crc32; + + Crc32 = ComputeCrc32(pMcAddress, ETHERNET_ADDRESS_SIZE); + + /* The most significant 7 bits of the CRC32 (no inversion), */ + /* are used to index into one of the possible 128 bit positions. */ + Bitpos = ~Crc32 & 0x7f; + + /* Hash register index. */ + RegIndex = (Bitpos & 0x60) >> 5; + + /* Bit to turn on within a hash register. */ + Bitpos &= 0x1f; + + /* Enable the multicast bit. */ + pDevice->MulticastHash[RegIndex] |= (1 << Bitpos); + + LM_SetReceiveMask(pDevice, pDevice->ReceiveMask | LM_ACCEPT_MULTICAST); + + return LM_STATUS_SUCCESS; +} + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +LM_STATUS +LM_MulticastDel(LM_DEVICE_BLOCK *pDevice, PLM_UINT8 pMcAddress) +{ + return LM_STATUS_FAILURE; +} /* LM_MulticastDel */ + + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +LM_STATUS +LM_MulticastClear(LM_DEVICE_BLOCK *pDevice) +{ + int i; + + for (i = 0; i < 4; i++) + { + pDevice->MulticastHash[i] = 0; + } + LM_SetReceiveMask(pDevice, pDevice->ReceiveMask & ~LM_ACCEPT_MULTICAST); + + return LM_STATUS_SUCCESS; +} /* LM_MulticastClear */ + + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +LM_STATUS +LM_SetMacAddress( + PLM_DEVICE_BLOCK pDevice, + PLM_UINT8 pMacAddress) +{ + LM_UINT32 j; + + for(j = 0; j < 4; j++) + { + REG_WR(pDevice, MacCtrl.MacAddr[j].High, + (pMacAddress[0] << 8) | pMacAddress[1]); + REG_WR(pDevice, MacCtrl.MacAddr[j].Low, + (pMacAddress[2] << 24) | (pMacAddress[3] << 16) | + (pMacAddress[4] << 8) | pMacAddress[5]); + } + + if ((T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700) && + (T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5701) && + (T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5705)) + { + for (j = 0; j < 12; j++) + { + REG_WR(pDevice, MacCtrl.MacAddrExt[j].High, + (pMacAddress[0] << 8) | pMacAddress[1]); + REG_WR(pDevice, MacCtrl.MacAddrExt[j].Low, + (pMacAddress[2] << 24) | (pMacAddress[3] << 16) | + (pMacAddress[4] << 8) | pMacAddress[5]); + } + } + return LM_STATUS_SUCCESS; +} + +LM_VOID +LM_PhyTapPowerMgmt(LM_DEVICE_BLOCK *pDevice) +{ + /* Turn off tap power management. */ + if((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5401_PHY_ID) + { + LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x4c20); + LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x0012); + LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x1804); + LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x0013); + LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x1204); + LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006); + LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0132); + LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006); + LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0232); + LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x201f); + LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0a20); + + MM_Wait(40); + } +} + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/* LM_STATUS_LINK_ACTIVE */ +/* LM_STATUS_LINK_DOWN */ +/******************************************************************************/ +static LM_STATUS +LM_InitBcm540xPhy( +PLM_DEVICE_BLOCK pDevice) +{ + LM_LINE_SPEED CurrentLineSpeed; + LM_DUPLEX_MODE CurrentDuplexMode; + LM_STATUS CurrentLinkStatus; + LM_UINT32 Value32; + LM_UINT32 j; + + LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x02); + + if ((pDevice->PhyFlags & PHY_RESET_ON_LINKDOWN) && + (pDevice->LinkStatus == LM_STATUS_LINK_ACTIVE)) + { + LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); + LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); + if(!(Value32 & PHY_STATUS_LINK_PASS)) + { + LM_ResetPhy(pDevice); + } + } + if((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5401_PHY_ID) + { + LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); + LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); + + if(!pDevice->InitDone) + { + Value32 = 0; + } + + if(!(Value32 & PHY_STATUS_LINK_PASS)) + { + LM_PhyTapPowerMgmt(pDevice); + + LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); + for(j = 0; j < 1000; j++) + { + MM_Wait(10); + + LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); + if(Value32 & PHY_STATUS_LINK_PASS) + { + MM_Wait(40); + break; + } + } + + if((pDevice->PhyId & PHY_ID_REV_MASK) == PHY_BCM5401_B0_REV) + { + if(!(Value32 & PHY_STATUS_LINK_PASS) && + (pDevice->OldLineSpeed == LM_LINE_SPEED_1000MBPS)) + { + LM_ResetPhy(pDevice); + } + } + } + } + else if(pDevice->ChipRevId == T3_CHIP_ID_5701_A0 || + pDevice->ChipRevId == T3_CHIP_ID_5701_B0) + { + /* Bug: 5701 A0, B0 TX CRC workaround. */ + LM_WritePhy(pDevice, 0x15, 0x0a75); + LM_WritePhy(pDevice, 0x1c, 0x8c68); + LM_WritePhy(pDevice, 0x1c, 0x8d68); + LM_WritePhy(pDevice, 0x1c, 0x8c68); + } + + /* Acknowledge interrupts. */ + LM_ReadPhy(pDevice, BCM540X_INT_STATUS_REG, &Value32); + LM_ReadPhy(pDevice, BCM540X_INT_STATUS_REG, &Value32); + + /* Configure the interrupt mask. */ + if(pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT) + { + LM_WritePhy(pDevice, BCM540X_INT_MASK_REG, ~BCM540X_INT_LINK_CHANGE); + } + + /* Configure PHY led mode. */ + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701 || + (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)) + { + if(pDevice->LedCtrl == LED_CTRL_PHY_MODE_1) + { + LM_WritePhy(pDevice, BCM540X_EXT_CTRL_REG, + BCM540X_EXT_CTRL_LINK3_LED_MODE); + } + else + { + LM_WritePhy(pDevice, BCM540X_EXT_CTRL_REG, 0); + } + } + + if (pDevice->PhyFlags & PHY_CAPACITIVE_COUPLING) + { + LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x4007); + LM_ReadPhy(pDevice, BCM5401_AUX_CTRL, &Value32); + if (!(Value32 & BIT_10)) + { + /* set the bit and re-link */ + LM_WritePhy(pDevice, BCM5401_AUX_CTRL, Value32 | BIT_10); + return LM_STATUS_LINK_SETTING_MISMATCH; + } + } + + CurrentLinkStatus = LM_STATUS_LINK_DOWN; + + /* Get current link and duplex mode. */ + for(j = 0; j < 100; j++) + { + LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); + LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); + + if(Value32 & PHY_STATUS_LINK_PASS) + { + break; + } + MM_Wait(40); + } + + if(Value32 & PHY_STATUS_LINK_PASS) + { + + /* Determine the current line and duplex settings. */ + LM_ReadPhy(pDevice, BCM540X_AUX_STATUS_REG, &Value32); + for(j = 0; j < 2000; j++) + { + MM_Wait(10); + + LM_ReadPhy(pDevice, BCM540X_AUX_STATUS_REG, &Value32); + if(Value32) + { + break; + } + } + + switch(Value32 & BCM540X_AUX_SPEED_MASK) + { + case BCM540X_AUX_10BASET_HD: + CurrentLineSpeed = LM_LINE_SPEED_10MBPS; + CurrentDuplexMode = LM_DUPLEX_MODE_HALF; + break; + + case BCM540X_AUX_10BASET_FD: + CurrentLineSpeed = LM_LINE_SPEED_10MBPS; + CurrentDuplexMode = LM_DUPLEX_MODE_FULL; + break; + + case BCM540X_AUX_100BASETX_HD: + CurrentLineSpeed = LM_LINE_SPEED_100MBPS; + CurrentDuplexMode = LM_DUPLEX_MODE_HALF; + break; + + case BCM540X_AUX_100BASETX_FD: + CurrentLineSpeed = LM_LINE_SPEED_100MBPS; + CurrentDuplexMode = LM_DUPLEX_MODE_FULL; + break; + + case BCM540X_AUX_100BASET_HD: + CurrentLineSpeed = LM_LINE_SPEED_1000MBPS; + CurrentDuplexMode = LM_DUPLEX_MODE_HALF; + break; + + case BCM540X_AUX_100BASET_FD: + CurrentLineSpeed = LM_LINE_SPEED_1000MBPS; + CurrentDuplexMode = LM_DUPLEX_MODE_FULL; + break; + + default: + + CurrentLineSpeed = LM_LINE_SPEED_UNKNOWN; + CurrentDuplexMode = LM_DUPLEX_MODE_UNKNOWN; + break; + } + + /* Make sure we are in auto-neg mode. */ + for (j = 0; j < 200; j++) + { + LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32); + if(Value32 && Value32 != 0x7fff) + { + break; + } + + if(Value32 == 0 && + pDevice->RequestedLineSpeed == LM_LINE_SPEED_10MBPS && + pDevice->RequestedDuplexMode == LM_DUPLEX_MODE_HALF) + { + break; + } + + MM_Wait(10); + } + + /* Use the current line settings for "auto" mode. */ + if(pDevice->RequestedLineSpeed == LM_LINE_SPEED_AUTO) + { + if(Value32 & PHY_CTRL_AUTO_NEG_ENABLE) + { + CurrentLinkStatus = LM_STATUS_LINK_ACTIVE; + + /* We may be exiting low power mode and the link is in */ + /* 10mb. In this case, we need to restart autoneg. */ + + if (LM_PhyAdvertiseAll(pDevice) != LM_STATUS_SUCCESS) + { + CurrentLinkStatus = LM_STATUS_LINK_SETTING_MISMATCH; + } + } + else + { + CurrentLinkStatus = LM_STATUS_LINK_SETTING_MISMATCH; + } + } + else + { + /* Force line settings. */ + /* Use the current setting if it matches the user's requested */ + /* setting. */ + LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32); + if((pDevice->LineSpeed == CurrentLineSpeed) && + (pDevice->DuplexMode == CurrentDuplexMode)) + { + if ((pDevice->DisableAutoNeg && + !(Value32 & PHY_CTRL_AUTO_NEG_ENABLE)) || + (!pDevice->DisableAutoNeg && + (Value32 & PHY_CTRL_AUTO_NEG_ENABLE))) + { + CurrentLinkStatus = LM_STATUS_LINK_ACTIVE; + } + else + { + CurrentLinkStatus = LM_STATUS_LINK_SETTING_MISMATCH; + } + } + else + { + CurrentLinkStatus = LM_STATUS_LINK_SETTING_MISMATCH; + } + } + + /* Save line settings. */ + pDevice->LineSpeed = CurrentLineSpeed; + pDevice->DuplexMode = CurrentDuplexMode; + } + + return CurrentLinkStatus; +} /* LM_InitBcm540xPhy */ + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +LM_STATUS +LM_SetFlowControl( + PLM_DEVICE_BLOCK pDevice, + LM_UINT32 LocalPhyAd, + LM_UINT32 RemotePhyAd) +{ + LM_FLOW_CONTROL FlowCap; + + /* Resolve flow control. */ + FlowCap = LM_FLOW_CONTROL_NONE; + + /* See Table 28B-3 of 802.3ab-1999 spec. */ + if(pDevice->FlowControlCap & LM_FLOW_CONTROL_AUTO_PAUSE) + { + if(LocalPhyAd & PHY_AN_AD_PAUSE_CAPABLE) + { + if(LocalPhyAd & PHY_AN_AD_ASYM_PAUSE) + { + if(RemotePhyAd & PHY_LINK_PARTNER_PAUSE_CAPABLE) + { + FlowCap = LM_FLOW_CONTROL_TRANSMIT_PAUSE | + LM_FLOW_CONTROL_RECEIVE_PAUSE; + } + else if(RemotePhyAd & PHY_LINK_PARTNER_ASYM_PAUSE) + { + FlowCap = LM_FLOW_CONTROL_RECEIVE_PAUSE; + } + } + else + { + if(RemotePhyAd & PHY_LINK_PARTNER_PAUSE_CAPABLE) + { + FlowCap = LM_FLOW_CONTROL_TRANSMIT_PAUSE | + LM_FLOW_CONTROL_RECEIVE_PAUSE; + } + } + } + else if(LocalPhyAd & PHY_AN_AD_ASYM_PAUSE) + { + if((RemotePhyAd & PHY_LINK_PARTNER_PAUSE_CAPABLE) && + (RemotePhyAd & PHY_LINK_PARTNER_ASYM_PAUSE)) + { + FlowCap = LM_FLOW_CONTROL_TRANSMIT_PAUSE; + } + } + } + else + { + FlowCap = pDevice->FlowControlCap; + } + + pDevice->FlowControl = LM_FLOW_CONTROL_NONE; + + /* Enable/disable rx PAUSE. */ + pDevice->RxMode &= ~RX_MODE_ENABLE_FLOW_CONTROL; + if(FlowCap & LM_FLOW_CONTROL_RECEIVE_PAUSE && + (pDevice->FlowControlCap == LM_FLOW_CONTROL_AUTO_PAUSE || + pDevice->FlowControlCap & LM_FLOW_CONTROL_RECEIVE_PAUSE)) + { + pDevice->FlowControl |= LM_FLOW_CONTROL_RECEIVE_PAUSE; + pDevice->RxMode |= RX_MODE_ENABLE_FLOW_CONTROL; + + } + REG_WR(pDevice, MacCtrl.RxMode, pDevice->RxMode); + + /* Enable/disable tx PAUSE. */ + pDevice->TxMode &= ~TX_MODE_ENABLE_FLOW_CONTROL; + if(FlowCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE && + (pDevice->FlowControlCap == LM_FLOW_CONTROL_AUTO_PAUSE || + pDevice->FlowControlCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE)) + { + pDevice->FlowControl |= LM_FLOW_CONTROL_TRANSMIT_PAUSE; + pDevice->TxMode |= TX_MODE_ENABLE_FLOW_CONTROL; + + } + REG_WR(pDevice, MacCtrl.TxMode, pDevice->TxMode); + + return LM_STATUS_SUCCESS; +} + + +#if INCLUDE_TBI_SUPPORT +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +STATIC LM_STATUS +LM_InitBcm800xPhy( + PLM_DEVICE_BLOCK pDevice) +{ + LM_UINT32 Value32; + LM_UINT32 j; + + Value32 = REG_RD(pDevice, MacCtrl.Status); + + /* Reset the SERDES during init and when we have link. */ + if(!pDevice->InitDone || Value32 & MAC_STATUS_PCS_SYNCED) + { + /* Set PLL lock range. */ + LM_WritePhy(pDevice, 0x16, 0x8007); + + /* Software reset. */ + LM_WritePhy(pDevice, 0x00, 0x8000); + + /* Wait for reset to complete. */ + for(j = 0; j < 500; j++) + { + MM_Wait(10); + } + + /* Config mode; seletct PMA/Ch 1 regs. */ + LM_WritePhy(pDevice, 0x10, 0x8411); + + /* Enable auto-lock and comdet, select txclk for tx. */ + LM_WritePhy(pDevice, 0x11, 0x0a10); + + LM_WritePhy(pDevice, 0x18, 0x00a0); + LM_WritePhy(pDevice, 0x16, 0x41ff); + + /* Assert and deassert POR. */ + LM_WritePhy(pDevice, 0x13, 0x0400); + MM_Wait(40); + LM_WritePhy(pDevice, 0x13, 0x0000); + + LM_WritePhy(pDevice, 0x11, 0x0a50); + MM_Wait(40); + LM_WritePhy(pDevice, 0x11, 0x0a10); + + /* Delay for signal to stabilize. */ + for(j = 0; j < 15000; j++) + { + MM_Wait(10); + } + + /* Deselect the channel register so we can read the PHY id later. */ + LM_WritePhy(pDevice, 0x10, 0x8011); + } + + return LM_STATUS_SUCCESS; +} + + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +STATIC LM_STATUS +LM_SetupFiberPhy( + PLM_DEVICE_BLOCK pDevice) +{ + LM_STATUS CurrentLinkStatus; + AUTONEG_STATUS AnStatus = 0; + LM_UINT32 Value32; + LM_UINT32 Cnt; + LM_UINT32 j, k; + LM_UINT32 MacStatus, RemotePhyAd, LocalPhyAd; + LM_FLOW_CONTROL PreviousFlowControl = pDevice->FlowControl; + + if (pDevice->LoopBackMode == LM_MAC_LOOP_BACK_MODE) + { + pDevice->LinkStatus = LM_STATUS_LINK_ACTIVE; + MM_IndicateStatus(pDevice, LM_STATUS_LINK_ACTIVE); + return LM_STATUS_SUCCESS; + } + + if ((T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5704) && + (pDevice->LinkStatus == LM_STATUS_LINK_ACTIVE) && pDevice->InitDone) + { + MacStatus = REG_RD(pDevice, MacCtrl.Status); + if ((MacStatus & (MAC_STATUS_PCS_SYNCED | MAC_STATUS_SIGNAL_DETECTED | + MAC_STATUS_CFG_CHANGED | MAC_STATUS_RECEIVING_CFG)) + == (MAC_STATUS_PCS_SYNCED | MAC_STATUS_SIGNAL_DETECTED)) + { + + REG_WR(pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED | + MAC_STATUS_CFG_CHANGED); + return LM_STATUS_SUCCESS; + } + } + pDevice->MacMode &= ~(MAC_MODE_HALF_DUPLEX | MAC_MODE_PORT_MODE_MASK); + + /* Initialize the send_config register. */ + REG_WR(pDevice, MacCtrl.TxAutoNeg, 0); + + /* Enable TBI and full duplex mode. */ + pDevice->MacMode |= MAC_MODE_PORT_MODE_TBI; + REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode); + + /* Initialize the BCM8002 SERDES PHY. */ + switch(pDevice->PhyId & PHY_ID_MASK) + { + case PHY_BCM8002_PHY_ID: + LM_InitBcm800xPhy(pDevice); + break; + + default: + break; + } + + /* Enable link change interrupt. */ + REG_WR(pDevice, MacCtrl.MacEvent, MAC_EVENT_ENABLE_LINK_STATE_CHANGED_ATTN); + + /* Default to link down. */ + CurrentLinkStatus = LM_STATUS_LINK_DOWN; + + /* Get the link status. */ + MacStatus = REG_RD(pDevice, MacCtrl.Status); + + if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704) + { + LM_UINT32 SgDigCtrl, SgDigStatus; + LM_UINT32 SerdesCfg = 0; + LM_UINT32 ExpectedSgDigCtrl = 0; + LM_UINT32 WorkAround = 0; + LM_UINT32 PortA = 1; + + if ((pDevice->ChipRevId != T3_CHIP_ID_5704_A0) && + (pDevice->ChipRevId != T3_CHIP_ID_5704_A1)) + { + WorkAround = 1; + if (REG_RD(pDevice, PciCfg.DualMacCtrl) & T3_DUAL_MAC_ID) + { + PortA = 0; + } + /* preserve the voltage regulator bits */ + SerdesCfg = REG_RD(pDevice, MacCtrl.SerdesCfg) & + (BIT_23 | BIT_22 | BIT_21 | BIT_20); + } + SgDigCtrl = REG_RD(pDevice, MacCtrl.SgDigControl); + if((pDevice->RequestedLineSpeed == LM_LINE_SPEED_AUTO) || + (pDevice->DisableAutoNeg == FALSE)) + { + + ExpectedSgDigCtrl = 0x81388400; + LocalPhyAd = GetPhyAdFlowCntrlSettings(pDevice); + if(LocalPhyAd & PHY_AN_AD_PAUSE_CAPABLE) + { + ExpectedSgDigCtrl |= BIT_11; + } + if(LocalPhyAd & PHY_AN_AD_ASYM_PAUSE) + { + ExpectedSgDigCtrl |= BIT_12; + } + if (SgDigCtrl != ExpectedSgDigCtrl) + { + if (WorkAround) + { + REG_WR(pDevice, MacCtrl.SerdesCfg, 0xc011880 | SerdesCfg); + } + REG_WR(pDevice, MacCtrl.SgDigControl, ExpectedSgDigCtrl | + BIT_30); + REG_RD_BACK(pDevice, MacCtrl.SgDigControl); + MM_Wait(5); + REG_WR(pDevice, MacCtrl.SgDigControl, ExpectedSgDigCtrl); + pDevice->AutoNegJustInited = TRUE; + } + /* If autoneg is off, you only get SD when link is up */ + else if(MacStatus & (MAC_STATUS_PCS_SYNCED | + MAC_STATUS_SIGNAL_DETECTED)) + { + SgDigStatus = REG_RD(pDevice, MacCtrl.SgDigStatus); + if ((SgDigStatus & BIT_1) && + (MacStatus & MAC_STATUS_PCS_SYNCED)) + { + /* autoneg. completed */ + RemotePhyAd = 0; + if(SgDigStatus & BIT_19) + { + RemotePhyAd |= PHY_LINK_PARTNER_PAUSE_CAPABLE; + } + + if(SgDigStatus & BIT_20) + { + RemotePhyAd |= PHY_LINK_PARTNER_ASYM_PAUSE; + } + + LM_SetFlowControl(pDevice, LocalPhyAd, RemotePhyAd); + CurrentLinkStatus = LM_STATUS_LINK_ACTIVE; + pDevice->AutoNegJustInited = FALSE; + } + else if (!(SgDigStatus & BIT_1)) + { + if (pDevice->AutoNegJustInited == TRUE) + { + /* we may be checking too soon, so check again */ + /* at the next poll interval */ + pDevice->AutoNegJustInited = FALSE; + } + else + { + /* autoneg. failed */ + if (WorkAround) + { + if (PortA) + { + REG_WR(pDevice, MacCtrl.SerdesCfg, + 0xc010880 | SerdesCfg); + } + else + { + REG_WR(pDevice, MacCtrl.SerdesCfg, + 0x4010880 | SerdesCfg); + } + } + /* turn off autoneg. to allow traffic to pass */ + REG_WR(pDevice, MacCtrl.SgDigControl, 0x01388400); + REG_RD_BACK(pDevice, MacCtrl.SgDigControl); + MM_Wait(40); + MacStatus = REG_RD(pDevice, MacCtrl.Status); + if (MacStatus & MAC_STATUS_PCS_SYNCED) + { + LM_SetFlowControl(pDevice, 0, 0); + CurrentLinkStatus = LM_STATUS_LINK_ACTIVE; + } + } + } + } + } + else + { + if (SgDigCtrl & BIT_31) { + if (WorkAround) + { + if (PortA) + { + REG_WR(pDevice, MacCtrl.SerdesCfg, + 0xc010880 | SerdesCfg); + } + else + { + REG_WR(pDevice, MacCtrl.SerdesCfg, + 0x4010880 | SerdesCfg); + } + } + REG_WR(pDevice, MacCtrl.SgDigControl, 0x01388400); + } + if(MacStatus & MAC_STATUS_PCS_SYNCED) + { + LM_SetFlowControl(pDevice, 0, 0); + CurrentLinkStatus = LM_STATUS_LINK_ACTIVE; + } + } + } + else if(MacStatus & MAC_STATUS_PCS_SYNCED) + { + if((pDevice->RequestedLineSpeed == LM_LINE_SPEED_AUTO) || + (pDevice->DisableAutoNeg == FALSE)) + { + /* auto-negotiation mode. */ + /* Initialize the autoneg default capaiblities. */ + AutonegInit(&pDevice->AnInfo); + + /* Set the context pointer to point to the main device structure. */ + pDevice->AnInfo.pContext = pDevice; + + /* Setup flow control advertisement register. */ + Value32 = GetPhyAdFlowCntrlSettings(pDevice); + if(Value32 & PHY_AN_AD_PAUSE_CAPABLE) + { + pDevice->AnInfo.mr_adv_sym_pause = 1; + } + else + { + pDevice->AnInfo.mr_adv_sym_pause = 0; + } + + if(Value32 & PHY_AN_AD_ASYM_PAUSE) + { + pDevice->AnInfo.mr_adv_asym_pause = 1; + } + else + { + pDevice->AnInfo.mr_adv_asym_pause = 0; + } + + /* Try to autoneg up to six times. */ + if (pDevice->IgnoreTbiLinkChange) + { + Cnt = 1; + } + else + { + Cnt = 6; + } + for (j = 0; j < Cnt; j++) + { + REG_WR(pDevice, MacCtrl.TxAutoNeg, 0); + + Value32 = pDevice->MacMode & ~MAC_MODE_PORT_MODE_MASK; + REG_WR(pDevice, MacCtrl.Mode, Value32); + REG_RD_BACK(pDevice, MacCtrl.Mode); + MM_Wait(20); + + REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode | + MAC_MODE_SEND_CONFIGS); + REG_RD_BACK(pDevice, MacCtrl.Mode); + + MM_Wait(20); + + pDevice->AnInfo.State = AN_STATE_UNKNOWN; + pDevice->AnInfo.CurrentTime_us = 0; + + REG_WR(pDevice, Grc.Timer, 0); + for(k = 0; (pDevice->AnInfo.CurrentTime_us < 75000) && + (k < 75000); k++) + { + AnStatus = Autoneg8023z(&pDevice->AnInfo); + + if((AnStatus == AUTONEG_STATUS_DONE) || + (AnStatus == AUTONEG_STATUS_FAILED)) + { + break; + } + + pDevice->AnInfo.CurrentTime_us = REG_RD(pDevice, Grc.Timer); + + } + if((AnStatus == AUTONEG_STATUS_DONE) || + (AnStatus == AUTONEG_STATUS_FAILED)) + { + break; + } + if (j >= 1) + { + if (!(REG_RD(pDevice, MacCtrl.Status) & + MAC_STATUS_PCS_SYNCED)) { + break; + } + } + } + + /* Stop sending configs. */ + MM_AnTxIdle(&pDevice->AnInfo); + + /* Resolve flow control settings. */ + if((AnStatus == AUTONEG_STATUS_DONE) && + pDevice->AnInfo.mr_an_complete && pDevice->AnInfo.mr_link_ok && + pDevice->AnInfo.mr_lp_adv_full_duplex) + { + LM_UINT32 RemotePhyAd; + LM_UINT32 LocalPhyAd; + + LocalPhyAd = 0; + if(pDevice->AnInfo.mr_adv_sym_pause) + { + LocalPhyAd |= PHY_AN_AD_PAUSE_CAPABLE; + } + + if(pDevice->AnInfo.mr_adv_asym_pause) + { + LocalPhyAd |= PHY_AN_AD_ASYM_PAUSE; + } + + RemotePhyAd = 0; + if(pDevice->AnInfo.mr_lp_adv_sym_pause) + { + RemotePhyAd |= PHY_LINK_PARTNER_PAUSE_CAPABLE; + } + + if(pDevice->AnInfo.mr_lp_adv_asym_pause) + { + RemotePhyAd |= PHY_LINK_PARTNER_ASYM_PAUSE; + } + + LM_SetFlowControl(pDevice, LocalPhyAd, RemotePhyAd); + + CurrentLinkStatus = LM_STATUS_LINK_ACTIVE; + } + else + { + LM_SetFlowControl(pDevice, 0, 0); + } + for (j = 0; j < 30; j++) + { + MM_Wait(20); + REG_WR(pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED | + MAC_STATUS_CFG_CHANGED); + REG_RD_BACK(pDevice, MacCtrl.Status); + MM_Wait(20); + if ((REG_RD(pDevice, MacCtrl.Status) & + (MAC_STATUS_SYNC_CHANGED | MAC_STATUS_CFG_CHANGED)) == 0) + break; + } + if (pDevice->TbiFlags & TBI_POLLING_FLAGS) + { + Value32 = REG_RD(pDevice, MacCtrl.Status); + if (Value32 & MAC_STATUS_RECEIVING_CFG) + { + pDevice->IgnoreTbiLinkChange = TRUE; + } + else if (pDevice->TbiFlags & TBI_POLLING_INTR_FLAG) + { + pDevice->IgnoreTbiLinkChange = FALSE; + } + } + Value32 = REG_RD(pDevice, MacCtrl.Status); + if (CurrentLinkStatus == LM_STATUS_LINK_DOWN && + (Value32 & MAC_STATUS_PCS_SYNCED) && + ((Value32 & MAC_STATUS_RECEIVING_CFG) == 0)) + { + CurrentLinkStatus = LM_STATUS_LINK_ACTIVE; + } + } + else + { + /* We are forcing line speed. */ + pDevice->FlowControlCap &= ~LM_FLOW_CONTROL_AUTO_PAUSE; + LM_SetFlowControl(pDevice, 0, 0); + + CurrentLinkStatus = LM_STATUS_LINK_ACTIVE; + REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode | + MAC_MODE_SEND_CONFIGS); + } + } + /* Se